 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| S1D13700 Embedded Memory Graphics LCD Controller Hardware Functional Specification Document Number: X42A-A-001-00 Status: Revision 1.0 Issue Date: 2004/01/06 Copyright (c) 2002, 2004 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 3 Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Features . . . . . . . . . 2.1 Internal Memory . . 2.2 Host CPU Interface . 2.3 Display Support . . . 2.4 Display Modes . . . 2.5 Character Generation 2.6 Power . . . . . . 2.7 Clock Source . . . . 2.8 Package . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . 12 . 12 . 12 . 12 . 12 . 13 . 13 . 13 . 13 2 3 4 5 System Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pins . . . . . . . . . . . . . . . . . 5.1 Pinout Diagram . . . . . . . . 5.2 Pin Descriptions . . . . . . . 5.2.1 Host Interface . . . . . . . . 5.2.2 LCD Interface . . . . . . . . 5.2.3 Clock Input . . . . . . . . . 5.2.4 Power And Ground . . . . . 5.3 Summary of Configuration Options 5.4 Host Bus Interface Pin Mapping . . . . . . . . . . ... .. .. ... ... ... ... .. .. .... .... .... ..... ..... ..... ..... .... .... ... .. .. ... ... ... ... .. .. . . . . . . . . . ...... ..... ..... ....... ....... ....... ....... ..... ..... . . . . . . . . . ....... ...... ...... ........ ........ ........ ........ ...... ...... 18 18 19 19 22 23 23 24 25 28 28 28 29 30 30 32 34 36 38 40 41 6 7 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Generic Bus Direct/Indirect Interface with WAIT# Timing . . . . . . . . . . . . . 7.3.2 Generic Bus Direct/Indirect Interface without WAIT# Timing . . . . . . . . . . . . 7.3.3 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing . . . . . . . . 7.3.4 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing . . . . . . 7.3.5 M6800 Family Bus Indirect Interface Timing . . . . . . . . . . . . . . . . . . . . 7.4 Power Save Mode/Display Enable Timing . . . . . . . . . . . . . . . . . . . 7.5 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 4 Epson Research and Development Vancouver Design Center 8 9 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Clocks . . . . . . . . . . . 9.1 Clock Diagram . . . . 9.2 Clock Descriptions . . 9.2.1 System Clock . . 9.2.2 FPSHIFT Clock . 9.3 Oscillator Circuit . . . . . . . . . ...... ..... ..... ....... ....... ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. ... ... .. ... .. .. .. ... ... ... ... ... .. ... ... ... ... ... ... ... ... ... ... ... ... ... .... .... .... ..... ..... .... .... .... .... .... ..... ..... ..... ..... .... .... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ... .. .. ... ... .. ... .. .. .. ... ... ... ... ... .. ... ... ... ... ... ... ... ... ... ... ... ... ... ... .. .. ... ... ... .. ... ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ..... ..... ....... ....... ..... ...... ..... ..... ..... ....... ....... ....... ....... ...... ..... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ..... ..... ....... ....... ....... ..... ....... ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 . . . . .45 . . . . .45 . . . . . . 45 . . . . . . 46 . . . . .46 . . . . . .47 . . . . .47 . . . . .48 . . . . .48 . . . . . . 48 . . . . . . 56 . . . . . . 69 . . . . . . 71 . . . . . .72 . . . . .73 . . . . . . 73 . . . . . . 73 . . . . . . 74 . . . . . . 75 . . . . . . 76 . . . . . . 76 . . . . . . 77 . . . . . . 77 . . . . . . 77 . . . . . . 78 . . . . . . 78 . . . . . . 78 . . . . . . 78 . . . . . .79 . . . . .79 . . . . .81 . . . . . . 81 . . . . . . 82 . . . . . . 85 . . . . .86 . . . . . . 86 . . . . . . 86 10 Registers . . . . . . . . . . . . . . . . 10.1 Register Set . . . . . . . . . . . 10.2 Register Restrictions . . . . . . . 10.3 Register Descriptions . . . . . . . 10.3.1 System Control Registers . . . . 10.3.2 Display Control Registers . . . . 10.3.3 Drawing Control Registers . . . 10.3.4 Gray Scale Register . . . . . . . 11 Indirect Addressing . . . 11.1 System Control . . . 11.1.1 SYSTEM SET . . 11.1.2 POWER SAVE . 11.1.3 DISP ON/OFF . . 11.1.4 SCROLL . . . . . 11.1.5 CSRFORM . . . 11.1.6 CSRDIR . . . . . 11.1.7 OVLAY . . . . . 11.1.8 CGRAM ADR . . 11.1.9 HDOT SCR . . . 11.1.10 CSRW . . . . . . 11.1.11 CSRR . . . . . . 11.1.12 GRAYSCALE . . 11.1.13 Memory Control . . . . . . . . . . . . . . . . ...... ..... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... 12 Display Control Functions . . . . . . . 12.1 Character Configuration . . . . . . 12.2 Screen Configuration . . . . . . . 12.2.1 Screen Configuration . . . . . . 12.2.2 Display Address Scanning . . . . 12.2.3 Display Scan Timing . . . . . . 12.3 Cursor Control . . . . . . . . . . 12.3.1 Cursor Write Register Function . 12.3.2 Cursor Movement . . . . . . . . ....... ...... ...... ........ ........ ........ ...... ........ ........ S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 5 12.3.3 Cursor Display Layers . . . . . . . . 12.4 Memory to Display Relationship . . . . 12.5 Scrolling . . . . . . . . . . . . . 12.5.1 On-Page Scrolling . . . . . . . . . . 12.5.2 Inter-Page Scrolling . . . . . . . . . 12.5.3 Horizontal Wraparound Scrolling . . 12.5.4 Bi-directional Scrolling . . . . . . . 12.5.5 Scroll Units . . . . . . . . . . . . . 13 Character Generator . . . . . . . . . . . . 13.1 CG Characteristics . . . . . . . . . 13.1.1 Internal Character Generator . . . . 13.1.2 Character Generator RAM . . . . . 13.2 Setting the Character Generator Address . 13.2.1 CGRAM Addressing Example . . . 13.3 Character Codes . . . . . . . . . . 14 Microprocessor Interface . . . . . 14.1 System Bus Interface . . . . . 14.1.1 Generic . . . . . . . . . . . 14.1.2 M6800 Family . . . . . . . . 14.1.3 MC68K Family . . . . . . . . . . . . . . . . . . . . ... .. .. ... ... ... ... ... . . . . . . . . ... .. .. ... ... ... ... ... ... .. ... ... .. ... .. ... .. ... ... ... . . . . . . . . . . . . . . . . . . . . ... .. .. ... ... ... ... ... . . . . . . . . ... .. .. ... ... ... ... ... . . . . . . . . . . . . . . . . . . . . ... .. .. ... ... ... ... ... . . . . . . . . ... .. .. ... ... ... ... ... . . . . . . . . 86 88 92 92 93 94 95 96 .... .... ..... ..... .... ..... .... ...... ..... ....... ....... ..... ....... ..... ...... ..... ....... ....... ....... . . . . . . . 97 . . . . . . 97 . . . . . . . . 97 . . . . . . . . 97 . . . . . . 98 . . . . . . . . 100 . . . . . . 101 . . . . . . . 102 . . . . . . 102 . . . . . . . . 102 . . . . . . . . 102 . . . . . . . . 102 ....... ...... ........ ........ ........ 15 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 15.1 Register Initialization/Initialization Parameters . . . . . . . . . . . . . . . . . 103 15.1.1 SYSTEM SET Command and Parameters . . . . . . . . . . . . . . . . . . . . . . 103 15.1.2 Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 15.1.3 Display Mode Setting Example 1: Combining Text and Graphics . . . . . . . . . . 110 15.1.4 Display Mode Setting Example 2: Combining Graphics and Graphics . . . . . . . . 112 15.1.5 Display Mode Setting Example 3: Combining Three Graphics Layers . . . . . . . . 114 15.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 15.3 Smooth Horizontal Scrolling . . . . . . . . . . . . . . . . . . . . . . . . 116 15.4 Layered Display Attributes . . . . . . . . . . . . . . . . . . . . . . . . . 118 15.4.1 Inverse Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 15.4.2 Half-Tone Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 15.4.3 Flash Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 15.5 16 16-Dot Graphic Display . . . . . . . . . . . . . . . . . . . . . . . . 121 15.5.1 Command Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 15.5.2 Kanji Character Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16 Internal Character Generator Font . . . . . . . . . . . . . . . . . . . . . . . . . . 125 17 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 18 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 6 Epson Research and Development Vancouver Design Center 19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 20 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 7 List of Tables Table 5-1: Cell Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5-2 Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . Table 5-3 LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . Table 5-4 Clock Input Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . Table 5-5 Power And Ground Pin Descriptions . . . . . . . . . . . . . . . . . . . Table 5-6: Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . Table 5-7: Host Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . Table 6-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . Table 6-2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . Table 6-3 Electrical Characteristics for VDD = 3.3V typical . . . . . . . . . . . . . Table 6-4 Electrical Characteristics for VDD = 5.0V typical . . . . . . . . . . . . . Table 6-5 Cell Type Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7-1 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . Table 7-2 Generic Bus Direct/Indirect Interface with WAIT# Timing . . . . . . . . Table 7-3 Generic Bus Direct/Indirect Interface without WAIT# Timing . . . . . . Table 7-4 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing . . Table 7-5 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing . Table 7-6 M6800 Family Bus Indirect Interface Timing . . . . . . . . . . . . . . . Table 7-7 Power Save Mode/Display Enable Timing. . . . . . . . . . . . . . . . . Table 7-8: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . Table 9-1 Crystal Oscillator Circuit Parameters . . . . . . . . . . . . . . . . . . . Table 10-1: S1D13700 Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10-2 LCD Parameter Summary . . . . . . . . . . . . . . . . . . . . . . . . . Table 10-3 Screen Block 3 Attribute Selection. . . . . . . . . . . . . . . . . . . . . Table 10-4 Screen Block 2/4 Attribute Selection . . . . . . . . . . . . . . . . . . . Table 10-5 Screen Block Attribute Selection. . . . . . . . . . . . . . . . . . . . . . Table 10-6 Cursor Flash Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . Table 10-7 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10-8 Cursor Shift Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10-9 Composition Method Selection . . . . . . . . . . . . . . . . . . . . . . Table 10-10 Bit-Per-Pixel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . Table 11-1 Indirect Addressing Command Set . . . . . . . . . . . . . . . . . . . . . Table 11-2 Generic Indirect Addressing Command/Write/Read. . . . . . . . . . . . Table 11-3 M6800 Indirect Addressing Command/Write/Read . . . . . . . . . . . . Table 11-4 M68K Indirect Addressing Command/Write/Read . . . . . . . . . . . . Table 11-5 SYSTEM SET Command and Parameters . . . . . . . . . . . . . . . . . Table 11-6 POWER SAVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 22 23 23 24 25 26 26 26 27 27 28 31 33 35 37 39 40 43 46 47 51 56 57 57 57 60 64 66 71 72 72 72 72 73 73 Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 8 Epson Research and Development Vancouver Design Center Table 11-7 DISP ON Command and Parameters . . . . . . . . . . . . . . . . . Table 11-8 DISP OFF Command and Parameters . . . . . . . . . . . . . . . . Table 11-9 SCROLL Command and Parameters . . . . . . . . . . . . . . . . . Table 11-10CSRFORM Command and Parameters. . . . . . . . . . . . . . . . Table 11-11CSRDIR Command. . . . . . . . . . . . . . . . . . . . . . . . . . Table 11-12OVLAY Command and Parameters . . . . . . . . . . . . . . . . . Table 11-13CGRAM ADR Command and Parameters . . . . . . . . . . . . . . Table 11-14HDOT SCR Command and Parameters . . . . . . . . . . . . . . . Table 11-15CSRW Command and Parameters . . . . . . . . . . . . . . . . . . Table 11-16CSRR Command and Parameters . . . . . . . . . . . . . . . . . . Table 11-17Gray Scale Command and Parameters . . . . . . . . . . . . . . . . Table 12-1 Scrolling Unit Summary . . . . . . . . . . . . . . . . . . . . . . . Table 13-1 Character Fonts Where Number of Lines 8 (REG[00h] bit 2 = 0) . Table 13-2 Character Fonts Where Number of Lines 16 (REG[00h] bit 2 = 1) Table 13-3 Character Data Example . . . . . . . . . . . . . . . . . . . . . . . Table 14-1 Generic Interface Signals . . . . . . . . . . . . . . . . . . . . . . . Table 14-2 M6800 Family Interface Signals . . . . . . . . . . . . . . . . . . . Table 14-3 M6800 Family Interface Signals . . . . . . . . . . . . . . . . . . . Table 15-1 Panel Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . Table 15-2 Indirect Addressing Initialization Procedure . . . . . . . . . . . . . Table 17-1 State of LCD Pins During Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 . 74 . 75 . 76 . 76 . 77 . 77 . 77 . 78 . 78 . 78 . 96 . 98 . 98 .100 .102 .102 .102 .104 .105 .126 S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 9 List of Figures Figure 3-1 Indirect Generic to S1D13700 Interface Example . . . . . . . . . . . . . . . . . . . Figure 3-2 Direct Generic to S1D13700 Interface Example . . . . . . . . . . . . . . . . . . . . Figure 3-3 Indirect MC68K to S1D13700 Interface Example . . . . . . . . . . . . . . . . . . . Figure 3-4 Direct MC68K to S1D13700 Interface Example . . . . . . . . . . . . . . . . . . . . Figure 3-5 Indirect M6800 to S1D13700 Interface Example . . . . . . . . . . . . . . . . . . . Figure 4-1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5-1 Pinout Diagram (TQFP13 - 64 pin). . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7-1 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7-2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7-3 Generic Bus Direct/Indirect Interface with WAIT# Timing . . . . . . . . . . . . . . Figure 7-4 Generic Bus Direct/Indirect Interface without WAIT# Timing . . . . . . . . . . . . Figure 7-5 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing. . . . . . . . . Figure 7-6 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing . . . . . . . Figure 7-7 M6800 Family Bus Indirect Interface Timing . . . . . . . . . . . . . . . . . . . . . Figure 7-8: Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 8-1 S1D13700 Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9-1: Clock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9-2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-1 Screen Origin Compensation and HDOT SCR Adjustment . . . . . . . . . . . . . . Figure 10-2 Single Drive Panel Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-3 Dual Drive Panel Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-4 Horizontal and Vertical Character Size Example . . . . . . . . . . . . . . . . . . . Figure 10-5 Horizontal Address Range and Character Bytes Per Row Relationship . . . . . . . . Figure 10-6 Dual Panel Display Height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-7 Cursor Size and Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-8 Cursor Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-9 Combined Layer Display Examples . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-10 Horizontal Scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12-1 Example of Character Display from Generator Bitmap (when [FX] 8) . . . . . . . Figure 12-2 Character Width Greater than One Byte Wide ([FX] = 9) . . . . . . . . . . . . . . . Figure 12-3 Virtual and Physical Screen Relationship . . . . . . . . . . . . . . . . . . . . . . . Figure 12-4 Display Addressing in Text Mode Example . . . . . . . . . . . . . . . . . . . . . . Figure 12-5 Display Addressing in Graphics Mode Example . . . . . . . . . . . . . . . . . . . . Figure 12-6 Dual Panel Display Address Indexing in Text Mode. . . . . . . . . . . . . . . . . . Figure 12-7 Relationship Between Total Character Bytes Per Row and Character Bytes Per Row Figure 12-8 Cursor Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12-9 Cursor Display Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 . 14 . 15 . 15 . 16 . 17 . 18 . 28 . 29 . 30 . 32 . 34 . 36 . 38 . 41 . 44 . 45 . 46 . 49 . 50 . 50 . 52 . 54 . 62 . 62 . 64 . 66 . 68 . 79 . 80 . 81 . 82 . 83 . 84 . 85 . 86 . 87 Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 10 Epson Research and Development Vancouver Design Center Figure 12-10 Cursor Movement . . . . . . . . . . . . . . . . . . . . . . . Figure 12-11 Screen Layers and Memory Relationship. . . . . . . . . . . Figure 12-12 Virtual Display (Display Window to Memory Relationship). Figure 12-13 Memory Map and Magnified Characters . . . . . . . . . . . Figure 12-14 On-Page Scrolling. . . . . . . . . . . . . . . . . . . . . . . Figure 12-15 Inter-Page Scrolling . . . . . . . . . . . . . . . . . . . . . . Figure 12-16 Horizontal Wraparound Scrolling. . . . . . . . . . . . . . . Figure 12-17 Bi-Directional Scrolling. . . . . . . . . . . . . . . . . . . . Figure 13-1 Row Select Address . . . . . . . . . . . . . . . . . . . . . . Figure 13-2 On-Chip Character Codes. . . . . . . . . . . . . . . . . . . Figure 15-1 Initialization Procedure . . . . . . . . . . . . . . . . . . . . Figure 15-2 Character Over Graphics Layers . . . . . . . . . . . . . . . Figure 15-3 Two-Layer Graphics . . . . . . . . . . . . . . . . . . . . . Figure 15-4 Three-Layer Graphics . . . . . . . . . . . . . . . . . . . . . Figure 15-5 HDOT SCR Example . . . . . . . . . . . . . . . . . . . . . Figure 15-6 Layer Synthesis . . . . . . . . . . . . . . . . . . . . . . . . Figure 15-7 Half-Tone Character And Graphics. . . . . . . . . . . . . . Figure 15-8 Flash Attribute for a Large Area . . . . . . . . . . . . . . . Figure 15-9 Graphics Address Indexing . . . . . . . . . . . . . . . . . . Figure 15-10 Graphics Bit Map . . . . . . . . . . . . . . . . . . . . . . . Figure 15-11 16 16-Dot Display Flowchart . . . . . . . . . . . . . . . . Figure 16-1 On-Chip Character Set . . . . . . . . . . . . . . . . . . . . Figure 18-1 Mechanical Drawing TQFP13 - 64 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 . .89 . .90 . .91 . .92 . .93 . .94 . .95 . .99 . 101 . 105 . 110 . 112 . 114 . 117 . 118 . 119 . 120 . 122 . 123 . 124 . 125 . 127 S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 11 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13700 Embedded Memory Graphics LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com. 1.2 Overview Description The S1D13700 Embedded Memory Graphics LCD Controller can display both text and graphics on an LCD panel. The S1D13700 allows layered text and graphics, scrolling of the display in any direction, and partitioning of the display into multiple screens. It includes 32K bytes of embedded SRAM display memory which is used to store text, character codes, and bit-mapped graphics. The S1D13700 handles display controller functions including: transferring data from the controlling microprocessor to the buffer memory, reading memory data, converting data to display pixels, and generating timing signals for the LCD panel. The S1D13700 is designed with an internal character generator which supports 160, 5x7 pixel characters in internal mask ROM (CGROM) and 64, 8x8 pixel characters in character generator RAM (CGRAM). When the CGROM is not used, up to 256, 8x16 pixel characters are supported in CGRAM. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 12 Epson Research and Development Vancouver Design Center 2 Features 2.1 Internal Memory * Embedded 32K bytes of SRAM display memory 2.2 Host CPU Interface * Direct Address Bus support for: * Generic Bus (Z80 family) microprocessor interface * MC68K family microprocessor interface * Indirect Address Bus support for: * Generic Bus (Z80 family) microprocessor interface * MC68K family microprocessor interface * M6800 family microprocessor interface * 8-bit CPU data bus interface 2.3 Display Support * 4-bit monochrome LCD interface * Maximum resolutions supported: 640x240 at 1 bpp 320x240 at 2 bpp 240x160 at 4 bpp * 1/2-duty to 1/256-duty LCD drive 2.4 Display Modes * 1/2/4 bit-per-pixel color depth support * Text, graphics and combined text/graphics display modes * Three overlapping screens in graphics mode * Programmable cursor control * Smooth horizontal scrolling of all or part of the display in monochrome mode * Smooth vertical scrolling of all or part of the display in all modes S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 13 2.5 Character Generation * 160, 5x7 pixel characters in embedded mask-programmed character generator ROM (CGROM) * Up to 64, 8x8 pixel characters in character generator RAM (CGRAM) * Up to 256, 8x16 pixel characters in embedded character generator RAM (when CGROM is not used) 2.6 Power * Software initiated power save mode * Low power consumption * CORE VDD 3.0 to 3.6 volts * IO VDD 3.0 to 5.5 volts 2.7 Clock Source * Two terminal crystal or Single Oscillator input Input Clock (maximum 60 MHz) FPSHIFT Clock (maximum 15 MHz) 2.8 Package * TQFP13 - 64-pin Pb-used package * TQFP13 - 64-pin Pb-free package (lead free) Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 14 Epson Research and Development Vancouver Design Center 3 System Diagrams Generic Bus (Indirect) S1D13700 CNF4 AS# CS# Axx Decoder CS# A[15:1] A0 D[15:8] D[7:0] RD0# RD1# WR0# WR1# WAIT# RESET# WAIT# RESET# CNF2 D[7:0] RD# WR# CNF3 A0 (command or parameter) /RESET Figure 3-1 Indirect Generic to S1D13700 Interface Example Generic Bus (Direct) S1D13700 CNF4 AS# CS# A[15:0] CS# A[15:0] D[15:8] D[7:0] RD0# RD1# WR0# WR1# WAIT# RESET# D[7:0] RD# WR# WAIT# RESET# CNF2 CNF3 /RESET Figure 3-2 Direct Generic to S1D13700 Interface Example S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 15 MC68K (Indirect) S1D13700 CNF4 AS# FC[2:0] A[23:1] AS# Decoder CS# A[15:1] A0 D[15:8] D[7:0] UDS# LDS# R/W# DTACK# RESET# A0 (command or parameter) D[7:0] RD# WR# WAIT# RESET# CNF2 CNF3 /RESET Figure 3-3 Indirect MC68K to S1D13700 Interface Example MC68K (Direct) S1D13700 CNF4 AS# FC[2:0] A[23:16] A[15:0] AS# Decoder CS# A[15:0] D[15:8] D[7:0] UDS# LDS# R/W# DTACK# RESET# D[7:0] RD# WR# WAIT# RESET# CNF2 CNF3 /RESET Figure 3-4 Direct MC68K to S1D13700 Interface Example Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 16 Epson Research and Development Vancouver Design Center M6800 (Indirect) S1D13700 CNF4 AS# VMA# Decoder CS# A[15:1] A0 (command or parameter) D[7:0] RD# WR# WAIT# CNF2 CNF3 A[16:1] A0 D[15:8] D[7:0] E R/W# RESET# RESET# /RESET Figure 3-5 Indirect M6800 to S1D13700 Interface Example S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 17 4 Functional Block Diagram LCD VideoRAM Character Generator RAM Character Generator ROM Video RAM Arbitrate FPDAT[3:0] FPSHIFT XECL YSCL FPLINE FPFRAME MOD YDIS LCD Controller Layered DotClock Generator Display Address Generator Cursor Address Controller Layered Controller GrayScale FRM Controller Dot Counter Internal Clock Microprocessor Interface Oscillator A0 to A15 D0 to D7 CS# RD# WR# AS# WAIT# CNF[4:0] RESET# XCG1 Host Microprocessor Figure 4-1 Functional Block Diagram Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 XCD1 CLKI Page 18 Epson Research and Development Vancouver Design Center 5 Pins 5.1 Pinout Diagram RD# COREVDD SCANEN HIOVDD RESET# TSTEN XCG1 WR# CLKI XCD1 48 D3 D2 D1 D0 VSS WAIT# HIOVDD CNF0 CNF1 CNF2 CNF3 CNF4 AS# A15 A14 A13 VSS 33 32 CS# D4 D5 D6 D7 49 NIOVDD YDIS FPFRAME YSCL VSS MOD FPLINE S1D13700 COREVDD XECL FPSHIFT NIOVDD FPDAT0 Index FPDAT1 FPDAT2 FPDAT3 64 17 1 16 VSS VSS COREVDD HIOVDD A9 A8 A7 A6 A5 A4 A3 A2 A1 A12 A11 Figure 5-1 Pinout Diagram (TQFP13 - 64 pin) S1D13700 X42A-A-001-00 Revision 1.0 A10 A0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 19 5.2 Pin Descriptions Key: Pin Types I O IO P RESET# States Z L H 0 1 = = = = Input Output Bi-Directional (Input/Output) Power pin = = = = = High Impedance (Hi-Z) Low level output High level output Pull-down control on input Pull-up control on input Table 5-1: Cell Descriptions Item SI CI CID1 CB2 OB2T LIN LOT T1 HTB2T CMOS level Schmitt input CMOS input CMOS input with internal pull-down resistor (typical value of 60k@5.0V) CMOS IO buffer (6mA/-6mA@3.3V, 8mA/-8mA@5.0V) Output buffer (6mA/-6mA@3.3V) with Test TTL transparent input TTL transparent output Test mode control input with pull-down resistor (typical value of 50 k@3.3V) Tri-state output buffer (6mA/-6mA@3.3V) Description 5.2.1 Host Interface Many of the host interface pins have different functions depending on the selection of the host bus interface (see configuration of CNF[4:2] pins in Table 5-6: "Summary of Configuration Options," on page 24). For a summary of host interface pins, see Table 5-7: "Host Interface Pin Mapping," on page 25. Table 5-2 Host Interface Pin Descriptions Pin Name Type Pin # 62-64, 2-6, 8-11, 13-15 Cell Power RESET# State System Address pins 15-1. CI HIOVDD Z * For Direct addressing mode, these pins are used for the system address bits 15-1. * For Indirect addressing mode, these pins must be connected to ground (VSS). Description A[15:1] I Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 20 Epson Research and Development Vancouver Design Center Table 5-2 Host Interface Pin Descriptions Pin Name Type Pin # Cell Power RESET# State System Address pin 0. A0 I 16 CI HIOVDD Z * For Direct addressing mode, this pin is used for system address bit 0. * For Indirect addressing mode, this pin in conjunction with RD# and WR# determines the type of data present on the data bus. System data bus pins 7-0. These tristate input/output data pins must be connected to the microprocessor data bus. These input pins are used for configuration of the FPSHIFT clock cycle time and must be connected to either HIOVDD or VSS. For further information, see Section 5.3, "Summary of Configuration Options" on page 24. These input pins select the host bus interface (microprocessor interface) and must be connected to either HIOVDD or VSS. The S1D13700 supports Generic processors (such as the 8085 and Z80(R)), the MC68K family of processors (such as the 68000) and the M6800 family of processors (such as the 6800). For further information, see Section 5.3, "Summary of Configuration Options" on page 24. This input pin selects the microprocessor addressing mode and must be connected to either HIOVDD or VSS. The S1D13700 supports both Direct and Indirect addressing modes. For further information, see Section 5.3, "Summary of Configuration Options" on page 24. This input pin has multiple functions. * When the Generic host bus interface is selected, this pin is the active-LOW read strobe (RD#). The S1D13700 data output buffers are enabled when this signal is low. * When the M6800 host bus interface is selected, this pin is the active-high enable clock (E). Data is read from or written to the S1D13700 when this clock goes high. * When the MC68K host bus interface is selected, this pin is the active-low lower data strobe (LDS#). Data is read from or written to the S1D13700 when this signal goes low. This input pin has multiple functions. * When the Generic host bus interface is selected, this signal is the active-low write strobe (WR#). The bus data is latched on the rising edge of this signal. * When the M6800 host bus interface is selected, this signal is the read/write control signal (R/W#). Data is read from the S1D13700 if this signal is high, and written to the S1D13700 if it is low. * When the MC68K host bus interface is selected, this signal is the read/write control signal (RD/WR#). Data is read from the S1D13700 if this signal is high, and written to the S1D13700 if it is low. Chip select. This active-low input enables the S1D13700. It is usually connected to the output of an address decoder device that maps the S1D13700 into the memory space of the controlling microprocessor. Description D[7:0] IO 44-47, 49-52 CB2 HIOVDD 0 or Z CNF[1:0] I 57, 56 SI HIOVDD Z CNF[3:2] I 59, 58 SI HIOVDD Z CNF4 I 60 SI HIOVDD Z RD# I 41 SI HIOVDD Z WR# I 42 SI HIOVDD Z CS# I 43 SI HIOVDD Z S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 21 Table 5-2 Host Interface Pin Descriptions Pin Name Type Pin # Cell Power RESET# State Description This output pin has multiple functions. * When the Generic host bus interface is selected, this pin is WAIT#. During a data transfer, WAIT# is driven active-low to force the system to insert wait states. It is driven inactive to indicate the completion of a data transfer. WAIT# is released to a high impedance state after the data transfer is complete. For indirect addressing mode, the WAIT# pin should be left unconnected and floating. * When the MC68K host bus interface is selected, this pin is DTACK#. During a data transfer, DTACK# is driven active-high to force the system to insert wait states. It is driven inactive to indicate the completion of a data transfer. DTACK# is released to a high impedance state after the data transfer is complete. For indirect addressing mode, DTACK# should be left unconnected and floating. * When the M6800 host bus interface is selected, this pin must be left unconnected and floating. This input pin has multiple functions. * When the Generic host bus interface is selected, this pin must be connected to VDD (pulled high). * When the MC68K host bus interface is selected, this pin is the address strobe (AS#). * When the M6800 host bus interface is selected, this pin must be connected to VDD (pulled high). This active-low input performs a hardware reset of the S1D13700 which sets all internal registers to their default states and forces all signals to their inactive states. Note: Do not trigger a RESET# when the supply voltage is lowered. SCANEN TSTEN I I 37 38 CID1 T1 HIOVDD HIOVDD 0 0 Reserved This pin must be connected to ground (VSS). Reserved This pin must be connected to ground (VSS). WAIT# O 54 HTB2T HIOVDD Z AS# I 61 CI HIOVDD Z RESET# I 36 SI HIOVDD Z Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 22 Epson Research and Development Vancouver Design Center 5.2.2 LCD Interface In order to provide effective low-power drive for LCD matrixes, the S1D13700 can directly control both the X and Y-drivers using an enable chain. Table 5-3 LCD Interface Pin Descriptions Pin Name FPDAT[3:0] (XD[3:0]) FPSHIFT (XSCL) XECL FPLINE (LP) MOD (WF) YSCL Type O Pin # 18-21 Cell OB2T Power NIOVDD RESET# State X Description These output pins are the 4-bit X-driver (column drive) data outputs and must be connected to the inputs of the X-driver chips. The falling edge of FPSHIFT latches the data on FPDAT[3:0] into the input shift registers of the X-drivers. To conserve power, this clock is stopped between FPLINE and the start of the following display line. The falling edge of XECL triggers the enable chain cascade for the X-drivers. Every 16th clock pulse is output to the next X-driver. FPLINE latches the signal in the X-driver shift registers into the output data latches. FPLINE is a falling edge triggered signal, and pulses once every display line. FPLINE must be connected to the Y-driver shift clock on LCD modules. This output pin is the LCD panel backplane bias signal. The MOD period is selected using the SYSTEM SET command. The falling edge of YSCL latches the data on FPFRAME into the input shift registers of the Y-drivers. YSCL is not used with driver ICs which use FPLINE as the Y-driver shift clock. This output pin is the data pulse output for the Y drivers. It is active during the last line of each frame, and is shifted through the Y drivers one by one (by YSCL), to scan the display's common connections. This output pin is the power-down output signal. YDIS is high while the display drive outputs are active. YDIS goes low one or two frames after the power save command is written to the S1D13700. All Y-driver outputs are forced to an intermediate level (deselecting the display segments) to blank the display. In order to implement power-down operation in the LCD unit, the LCD power drive supplies must also be disabled when the display is disabled by YDIS. O 23 OB2T NIOVDD X O 24 OB2T NIOVDD X O 26 OB2T NIOVDD X O O 27 29 OB2T OB2T NIOVDD NIOVDD X X FPFRAME (YD) O 30 OB2T NIOVDD X YDIS O 31 OB2T NIOVDD L S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 23 5.2.3 Clock Input Table 5-4 Clock Input Pin Descriptions Pin Name Type Pin # Cell Power RESET# State Z Description This input pin is the crystal connection for use with the internal oscillator. This pin must be pulled down when using an external clock source (CLKI). For further information on the use of the internal oscillator, see Section 9.3, "Oscillator Circuit" on page 46. This output pin is the crystal connection for use with the internal oscillator. This pin must be left unconnected when using an external clock source (CLKI). For further information on the use of the internal oscillator, see Section 9.3, "Oscillator Circuit" on page 46. This is the external clock input. This pin must be pulled down when using a crystal with the internal oscillator. For further information on clocks, see Section 9, "Clocks" on page 45. XCG1 I 35 LIN COREVDD XCD1 O 34 LOT COREVDD -- CLKI I 39 CI HIOVDD Z 5.2.4 Power And Ground Table 5-5 Power And Ground Pin Descriptions Pin Name HIOVDD NIOVDD COREVDD VSS Type P P P P Pin # 55, 48, 7 32, 22 40, 25, 12 53, 33, 28, 17, 1 Cell P P P P Power -- -- -- -- RESET# State -- -- -- -- Description IO power supply for the Host (MPU) interface, 3.3/5.0 volts. IO power supply for the LCD interface, 3.3/5.0 volts. Core power supply, 3.3 volts. Ground for HIOVDD, NIOVDD, and COREVDD Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 24 Epson Research and Development Vancouver Design Center 5.3 Summary of Configuration Options These pins are used for configuration of the chip and must be connected directly to HIOVDD or VSS. Note The state of CNF[4:0] can be set at any time before or during operation of the S1D13700. Table 5-6: Summary of Configuration Options Configuration Input Configuration State 1 (connected to HIOVDD) Indirect Addressing Mode: 1-bit address bus 8-bit data bus 9 pins are used 0 (connected to VSS) DIrect Addressing Mode: 16-bit address bus 8-bit data bus 24 pins are used CNF4 CNF[3:2] Select the host bus interface as follows: CNF3 CNF2 Host Bus 0 0 Generic Bus 0 1 Reserved 1 0 M6800 Family Bus Interface 1 1 MC68K Family Bus Interface Select the FPSHIFT cycle time (FPSHIFT:Clock Input) as follows: CNF1 CNF0 FPSHIFT Cycle Time 0 0 4:1 0 1 8:1 1 0 16:1 1 1 Reserved CNF[1:0] S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 25 5.4 Host Bus Interface Pin Mapping Table 5-7: Host Interface Pin Mapping Pin Name AB[15:1] AB0 DB[7:0] CS# AS# RD# WR# WAIT# RESET# CNF4 CNF3 CNF2 CNF[1:0] Generic Direct A[15:1] A0 D[7:0] CS# Generic Indirect Connected to VSS A0 D[7:0] CS# MC68K Direct A[15:1] A0 D[7:0] External Decode AS# LDS# RD/WR# RESET# MC68K Indirect Connected to VSS A0 D[7:0] External Decode AS# LDS# RD/WR# RESET# Not supported M6800 Direct M6800 Indirect Connected to VSS A0 D[7:0] External Decode Connected to VSS E R/W# Unconnected RESET# Connected to HIOVDD Connected to HIOVDD Connected to VSS See Note Connected to Connected to HIOVDD HIOVDD RD# WR# RESET# RD# WR# RESET# WAIT# or Unconnected DTACK# or Unconnected Connected to Connected to Connected to Connected to VSS HIOVDD VSS HIOVDD Connected to Connected to Connected to Connected to VSS VSS HIOVDD HIOVDD Connected to Connected to Connected to Connected to VSS VSS HIOVDD HIOVDD See Note See Note See Note See Note Note CNF[1:0] are used to configure the FPSHIFT cycle time and must be set according to the requirements of the specific implementation. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 26 Epson Research and Development Vancouver Design Center 6 D.C. Characteristics Table 6-1 Absolute Maximum Ratings Symbol CORE VDD IO VDD VIN VOUT TSTG TSOL Parameter Supply Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature Solder Temperature/Time VSS - 0.3 to 4.0 VSS - 0.3 to 7.0 VSS - 0.3 to IO VDD + 0.5 VSS - 0.3 to IO VDD + 0.5 -65 to 150 260 for 10 sec. max at lead Rating Units V V V V C C Table 6-2 Recommended Operating Conditions Symbol Core VDD HIO VDD NIO VDD HIO VIN NIO VIN TOPR Parameter Supply Voltage Host Bus IO Supply Voltage Panel IO Supply Voltage Host Input Voltage Non-Host Input Voltage Operating Temperature Condition VSS = 0 V VSS = 0 V VSS = 0 V 3.0 3.0 4.5 3.0 4.5 VSS VSS -40 25 Min 3.3 3.3 5.0 3.3 5.0 Typ 3.6 3.6 5.5 3.6 5.5 HIO VDD NIO VDD 85 Max Units V V V V V V V C Table 6-3 Electrical Characteristics for VDD = 3.3V typical Symbol IQH ILZ IOZ VOH VOL VIH1 VIL1 VT+ VTVH1 RPD Parameter Core Quiescent Current IO Quiescent Current Input Leakage Current Output Leakage Current High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Voltage Hysteresis Voltage Pull Down Resistance Condition Power save mode enabled Power save mode enabled Min Typ -1 -1 50 Max 35 30 1 1 Units A A A A V V V V V V V k VDD = min. IOH = -6mA VDD = min. IOL = 6mA LVTTL Level, VDD = max LVTTL Level, VDD = min. LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt VI = VDD VDD-0.4 0.4 2.0 1.1 0.6 0.1 20 0.8 2.4 1.8 120 S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 27 Table 6-4 Electrical Characteristics for VDD = 5.0V typical Symbol IQH ILZ IOZ VOH VOL VIH VIL VT+ VTVH RPD Parameter Core Quiescent Current IO Quiescent Current Input Leakage Current Output Leakage Current High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Voltage Hysteresis Voltage Pull Down Resistance Condition Power save mode enabled Power save mode enabled Min Typ -1 -1 60 Max 35 30 1 1 Units A A A A V V V V V V V k VDD = min. -8mA IOH = VDD = min. 8mA IOL = CMOS Level, VDD = max CMOS Level, VDD = min. CMOS Schmitt CMOS Schmitt CMOS Schmitt VI = VDD VDD-0.4 0.4 3.5 2.0 0.8 0.3 30 1.0 4.0 3.1 144 The following electrical characteristics from Table 6-3 "Electrical Characteristics for VDD = 3.3V typical," on page 26 and Table 6-4 "Electrical Characteristics for VDD = 5.0V typical," on page 27 apply to the following cell types. Table 6-5 Cell Type Reference Electrical Characteristic VOH / VOL Cell Type OB2T CB2 HTB2T CI CID1 CB2 SI SI CID1 VIH / VIL VT+ / VTVH RPD Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 28 Epson Research and Development Vancouver Design Center 7 A.C. Characteristics Conditions: Core VDD = 3.3V 10% IO VDD = 3.3V 10% or 5.0V 10% TOPR = -40 C to 85 C Trise and Tfall for all inputs must be < 5 nsec (10% ~ 90%) CL = 30pF (Bus/MPU Interface) CL = 30pF (LCD Panel Interface) Note CL includes a maximum pin capacitance of 5pF. 7.1 Clock Timing 7.1.1 Input Clock Clock Input Waveform t t PWH PWL 90% V IH VIL 10% tr t TCLKI f Figure 7-1 Clock Input Requirements Table 7-1 Clock Input Requirements Symbol fCLKI TCLKI tPWH tPWL tf tr Parameter Input Clock Frequency (CLKI) Input Clock period (CLKI) Input Clock Pulse Width High (CLKI) Input Clock Pulse Width Low (CLKI) Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) 3.0V Min Max 60 Min 5.0V Max 60 Units MHz ns ns ns ns ns 1/fOSC 0.4TCLKI 0.4TCLKI 1/fOSC 0.4TCLKI 0.4TCLKI 2 2 2 2 Note Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI. For further details on internal clocks, see Section 9, "Clocks" on page 45. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 29 7.2 Reset Timing VDD 1ms RESET# 0.7 VDD 0.3 VDD Figure 7-2 Reset Timing The S1D13700 requires a reset pulse of at least 1 ms after power-on in order to re-initialize its internal state. For maximum reliability, it is not recommended to apply a DC voltage to the LCD panel while the S1D13700 is reset. Turn off the LCD power supplies for at least one frame period after the start of the reset pulse. During the reset period the S1D13700 cannot receive commands. Commands to initialize the internal registers should be issued soon after a reset. During reset, the LCD drive signals FPDAT, FPLINE and FR are halted. A delay of 3 ms (maximum) is required following the rising edges of both RESET# and VDD to allow for system stabilization. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 30 Epson Research and Development Vancouver Design Center 7.3 CPU Interface Timing 7.3.1 Generic Bus Direct/Indirect Interface with WAIT# Timing t1 CS# t2 AB[15:0] t13 t14 WR#, RD# t3 WAIT# t4 DB[7:0] (write) t5 DB[7:0] (read) t12 Valid t6 t7 t15 t16 t8 t9 t11 t10 Valid Figure 7-3 Generic Bus Direct/Indirect Interface with WAIT# Timing S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 31 Table 7-2 Generic Bus Direct/Indirect Interface with WAIT# Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 CS# setup time AB[15:0] setup time WR#, RD# falling edge to WAIT# driven low DB[7:0] setup time to WR# rising edge (write cycle) RD# falling edge to DB[7:0] driven (read cycle) CS# hold time AB[15:0] hold time RD#, WR# rising edge to WAIT# high impedance DB[7:0] hold time from WR# rising edge (write cycle) DB[7:0] hold time from RD# rising edge (read cycle) WAIT# rising edge to valid Data if WAIT# is used RD# falling edge to valid Data if WAIT# is not used RD#, WR# cycle time RD#, WR# pulse active time RD#, WR# pulse inactive time WAIT# pulse active time Parameter 3.3 Volt Min 5 5 2 Note 2 3 7 7 2 5 3 Max 5.0 Volt Min 5 5 2 Note 2 3 7 7 2 5 3 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns Ts ns ns 15 15 10 10 14 Note 3 Note 4 14 Note 3 Note 4 Note 5 5 Note 6 Note 5 5 Note 6 Note 7 Note 7 1. Ts = System clock period 2. t4min = 2Ts + 5 3. t11max = 1Ts + 5 (for 3.3V) = 1Ts + 7 (for 5.0V) 4. t12max = 4Ts + 18 (for 3.3V) = 4Ts + 20 (for 5.0V) 5. t13min = 6Ts (for a read cycle followed by a read or write cycle) = 7Ts + 2 (for a write cycle followed by a write cycle) = 10Ts + 2 (for a write cycle followed by a read cycle) 6. t15min = 1Ts (for a read cycle followed by a read or write cycle) = 2Ts + 2 (for a write cycle followed by a write cycle) = 5Ts + 2 (for a write cycle followed by a read cycle) 7. t16max = 4Ts + 2 Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 32 Epson Research and Development Vancouver Design Center 7.3.2 Generic Bus Direct/Indirect Interface without WAIT# Timing t1 CS# t2 AB[15:0] t10 t11 WR#, RD# t5 t6 t12 t3 DB[7:0] (write) t4 DB[7:0] (read) t9 Valid t7 t8 Valid Figure 7-4 Generic Bus Direct/Indirect Interface without WAIT# Timing S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 33 Table 7-3 Generic Bus Direct/Indirect Interface without WAIT# Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 CS# setup time AB[15:0] setup time DB[7:0] setup time to WR# rising edge (write cycle) RD# falling edge to DB[7:0] driven (read cycle) CS# hold time AB[15:0] hold time DB[7:0] hold time from WR# rising edge (write cycle) DB[7:0] hold time from RD# rising edge (read cycle) RD# falling edge to valid Data (read cycle) RD#, WR# cycle time RD#, WR# pulse active time RD#, WR# pulse inactive time Parameter 3.3 Volt Min 5 5 Note 2 3 7 7 5 3 Max 5.0 Volt Min 5 5 Note 2 3 7 7 5 3 Max Units ns ns ns ns ns ns ns ns ns ns Ts ns 14 Note 3 14 Note 3 Note 4 5 Note 5 Note 4 5 Note 5 1. Ts = System clock period 2. t3min = 2Ts + 5 3. t9max = 4Ts + 18 (for 3.3V) = 4Ts + 20 (for 5.0V) 4. t10min = 6Ts (for a read cycle followed by a read or write cycle) = 7Ts + 2 (for a write cycle followed by a write cycle) = 10Ts + 2 (for a write cycle followed by a read cycle) 5. t12min = 1Ts (for a read cycle followed by a read or write cycle) = 2Ts + 2 (for a write cycle followed by a write cycle) = 5Ts + 2 (for a write cycle followed by a read cycle) Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 34 Epson Research and Development Vancouver Design Center 7.3.3 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing t1 CS# t2 AB[15:0], WR# (RW#, MR#) t17 AS# t13 t14 RD# (UDS#, LDS#) t19 t3 WAIT# (DTACK#) t4 DB[7:0] (write) t5 DB[7:0] (read) t12 t11 t10 t9 t16 t8 t20 t15 t18 t7 t6 Figure 7-5 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 35 Table 7-4 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 CS# setup time AB[15:0] setup time AS# falling edge to WAIT# driven DB[7:0] setup time to RD# rising edge (write cycle) RD# falling edge to DB[7:0] driven (read cycle) CS# hold time AB[15:0] hold time RD# rising edge to WAIT# high impedance if Direct interface and in Power Save Mode DB[7:0] hold time from RD# rising edge (write cycle) DB[7:0] hold time from RD# rising edge (read cycle) WAIT# falling edge to valid Data if WAIT# is used RD# falling edge to valid Data if WAIT# is not used RD# cycle time RD# pulse active time RD# pulse inactive time WAIT# pulse inactive time from WAIT# driven AS# setup time AS# hold time AS# rising edge to WAIT# high de-asserted if not Direct interface and not in Power Save Mode WAIT# pulse inactive time Parameter 3.3 Volt Min 5 5 2 Note 2 3 7 7 2 5 2 Max 5.0 Volt Min 5 5 2 Note 2 3 7 7 2 5 2 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns Ts ns ns ns ns ns ns 15 15 10 10 55 Note 3 Note 4 55 Note 3 Note 4 Note 5 5 Note 6 Note 5 5 Note 6 Note 7 Note 7 0 0 0 0 10 Note 8 10 Note 8 0 0 1. Ts = System clock period 2. t4min = 2Ts + 5 3. t11max = 1Ts + 5 (for 3.3V) = 1Ts + 7 (for 5.0V) 4. t12max = 4Ts + 18 (for 3.3V) = 4Ts + 20 (for 5.0V) 5. t13min = 6Ts (for a read cycle followed by a read or write cycle) = 7Ts + 2 (for a write cycle followed by a write cycle) = 10Ts + 2 (for a write cycle followed by a read cycle) 6. t15min = 1Ts (for a read cycle followed by a read or write cycle) = 2Ts + 2 (for a write cycle followed by a write cycle) = 5Ts + 2 (for a write cycle followed by a read cycle) 7. t16max = 4Ts + 2 8. t20max = 1Ts - 15 Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 36 Epson Research and Development Vancouver Design Center 7.3.4 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing t1 CS# t2 AB[15:0], WR# (RW#, MR#) t13 AS# t10 t11 RD# (UDS#, LDS#) t3 DB[7:0] (write) t4 DB[7:0] (read) t9 t8 t7 t12 t14 t6 t5 Figure 7-6 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 37 Table 7-5 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 CS# setup time AB[15:0] setup time DB[7:0] setup time to RD# rising edge (write cycle) RD# falling edge to DB[7:0] driven (read cycle) CS# hold time AB[15:0] hold time DB[7:0] hold time from RD# rising edge (write cycle) DB[7:0] hold time from RD# rising edge (read cycle) RD# falling edge to valid Data RD# cycle time RD# pulse active time RD# pulse inactive time AS# setup time AS# hold time Parameter 3.3 Volt Min 5 5 Note 2 3 7 7 5 2 Max 5.0 Volt Min 5 5 Note 2 3 7 7 5 2 Max Units ns ns ns ns ns ns ns ns ns ns Ts ns ns ns 55 Note 3 55 Note 3 Note 4 5 Note 5 0 0 Note 4 5 Note 5 0 0 1. Ts = System clock period 2. t3min = 2Ts + 5 3. t9max = 4Ts + 18 (for 3.3V) = 4Ts + 20 (for 5.0V) 4. t13min = 6Ts (for a read cycle followed by a read or write cycle) = 7Ts + 2 (for a write cycle followed by a write cycle) = 10Ts + 2 (for a write cycle followed by a read cycle) 6. t15min = 1Ts (for a read cycle followed by a read or write cycle) = 2Ts + 2 (for a write cycle followed by a write cycle) = 5Ts + 2 (for a write cycle followed by a read cycle) Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 38 Epson Research and Development Vancouver Design Center 7.3.5 M6800 Family Bus Indirect Interface Timing t1 CS# t2 AB[15:0], WR# (RW#, MR#) t13 AS# t10 t11 RD# (UDS#, LDS#) t3 DB[7:0] (write) t4 DB[7:0] (read) t9 t8 t7 t12 t14 t6 t5 Figure 7-7 M6800 Family Bus Indirect Interface Timing Note CLK input to the M6800 interface must be driven synchronous to the host microprocessor. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 39 Table 7-6 M6800 Family Bus Indirect Interface Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 CS# setup time AB[15:0] setup time DB[7:0] setup time to RD# falling edge (write cycle) RD# rising edge to DB[7:0] driven (read cycle) CS# hold time AB[15:0] hold time DB[7:0] hold time from RD# falling edge (write cycle) DB[7:0] hold time from RD# falling edge (read cycle) RD# rising edge to valid Data RD# cycle time RD# pulse active time RD# pulse inactive time AS# setup time AS# hold time Parameter 3.3 Volt Min 5 5 Note 2 3 7 7 5 2 Max 5.0 Volt Min 5 5 Note 2 3 7 7 5 2 Max Units ns ns ns ns ns ns ns ns ns ns Ts ns ns ns 55 Note 3 55 Note 3 Note 4 5 Note 5 0 0 Note 4 5 Note 5 0 0 1. Ts = System clock period 2. t3min = 2Ts + 5 3. t9max = 4Ts + 18 (for 3.3V) = 4Ts + 20 (for 5.0V) 4. t13min = 6Ts (for a read cycle followed by a read or write cycle) = 7Ts + 2 (for a write cycle followed by a write cycle) = 10Ts + 2 (for a write cycle followed by a read cycle) 6. t15min = 1Ts (for a read cycle followed by a read or write cycle) = 2Ts + 2 (for a write cycle followed by a write cycle) = 5Ts + 2 (for a write cycle followed by a read cycle) Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 40 Epson Research and Development Vancouver Design Center 7.4 Power Save Mode/Display Enable Timing WR# t1 t2 YDIS Display On Display Off or Power Save Mode Enabled Display On Table 7-7 Power Save Mode/Display Enable Timing Symbol Parameter YDIS falling edge delay for Power Save Mode Enable in Indirect Mode (see Note 2) YDIS falling edge delay for Display Off in Indirect Mode (58h) YDIS falling edge delay for Display Off in Direct Mode (see Note 3) YDIS rising edge delay for Display On (see Note 3) 3.0 Volt Min. Max. 2 1Ts + 10 2Ts + 10 2Ts + 10 Min. 5.0 Volt Max. 2 1Ts + 10 2Ts + 10 2Ts + 10 Units t1a t1b t1c t2 Frames ns ns ns 1. Ts = System Clock Period 2. Power Save Mode is controlled by the Power Save Mode Enable bit, REG[08h] bit 0. 3. Display On/Off is controlled by the Display Enable bit, REG[09h] bit 0. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 41 7.5 Display Interface The timing parameters required to drive a flat panel display are shown below. VDP (1 Frame) FPFRAME (YD) FPLINE (LP) MOD (WF) FPDAT[3:0] YSCL Invalid LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 Invalid LINE1 LINE2 MOD YSCL FPLINE (LP) HNDP 1 Line HDP HNDP FPSHIFT (XSCL) FPDAT3 FPDAT2 FPDAT1 FPDAT0 XECL Invalid Invalid Invalid Invalid 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-317 1-318 1-319 1-320 Invalid Invalid Invalid Invalid Figure 7-8: Monochrome 4-Bit Panel Timing Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 42 Epson Research and Development Vancouver Design Center t1 FPSHIFT (XSCL) t2 t3 t4 FPDAT3 t5 FPDAT2 FPDAT1 FPDAT0 t6 FPLINE (LP) t7 t8 t9 t10 XECL t11 t12 MOD (WF(B)) t13 FPFRAME (YD) t14 t15 YSCL t16 S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 43 Table 7-8: Single Monochrome 4-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 FPSHIFT cycle time FPSHIFT pulse width Latch data setup time from FPSHIFT falling edge FPDAT[3:0] setup to FPSHIFT falling edge FPDAT[3:0] hold from FPSHIFT falling edge FPLINE rising edge delay from FPSHIFT rising edge Latch pulse width XECL falling edge setup time to FPSHIFT falling edge XECL falling edge setup time from FPLINE rising edge XECL falling edge hold time to FPLINE falling edge XECL pulse width Permitted MOD delay time FPLINE falling edge from FPFRAME rising edge FPLINE falling edge to FPFRAME falling edge FPFRAME falling edge hold time from YSCL falling edge YSCL pulse width Parameter 3.3 Volts Min Max 1 0.5Tc - 5 0.5Tc - 5 0.5Tc - 5 0.5Tc - 5 0 Tc - 5 0.25Tc -5 0.75Tc - 5 Tc - 8 0.75Tc - 5 5.0 Volts Min Max 1 0.5Tc - 4 0.5Tc - 4 0.5Tc - 4 0.5Tc - 4 0 Tc - 4 0.25Tc - 4 0.75Tc - 4 Tc - 8 0.75Tc - 4 Units Tc (Note 2) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 4 4 4 2Tc - 10 2Tc 3Tc - 10 Tc - 5 2Tc - 10 2Tc 3Tc - 10 Tc - 4 1. Ts 2. Tc = System clock period = FPSHIFT cycle time = 4Ts when CNF[1:0] = 00 = 8Ts when CNF[1:0] = 01 = 16Ts when CNF[1:0] = 10 Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 44 Epson Research and Development Vancouver Design Center 8 Memory Mapping The S1D13700 includes 32K bytes of embedded SRAM. The memory is used for the display data, the registers and the CGROM. (MSB) D7 0000h D0 DISPLAY RAM Area 7FFFh 8000h Register Area 802Fh 8030h Not Used FFFFh Figure 8-1 S1D13700 Memory Mapping S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 45 9 Clocks 9.1 Clock Diagram The following figure shows the clock tree of the S1D13700. System Clock CLKI FPSHIFT Clock DIV Internal OSC Power Save Mode (REG[08h] bit 0) FPSHIFT Cycle Time (CNF[1:0] see Note) Figure 9-1: Clock Diagram Note The FPSHIFT Cycle Time is configured using the CNF[1:0] pins. For further information, see Section 5.3, "Summary of Configuration Options" on page 24. 9.2 Clock Descriptions 9.2.1 System Clock The maximum frequency of the system clock is 60MHz. The system clock source can be either an external clock source (i.e. oscillator) or the internal crystal. If an external clock source is used, the crystal input (XCG1) must be pulled down and the crystal output (XCD1) must be left unconnected. If the internal crystal is used, the CLKI pin must be pulled down. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 46 Epson Research and Development Vancouver Design Center 9.2.2 FPSHIFT Clock The FPSHIFT clock is derived from the internal system clock as shown in Figure 9-1: "Clock Diagram," on page 45. The maximum frequency possible for FPSHIFT clock is 15MHz. 9.3 Oscillator Circuit The S1D13700 design incorporates an oscillator circuit. A stable oscillator can be constructed by connecting an AT-cut crystal, two capacitors, and two resistors to XCG1 and XCD1, as shown in the figure below. If the oscillator frequency is increased, Cd and Cg should be decreased proportionally. Note The circuit board lines to XCG1 and XCD1 must be as short as possible to prevent wiring capacitance from changing the oscillator frequency or increasing the power consumption. S1D13700 XCG1 XCD1 Rf Rd Xtal Cg Cd Figure 9-2 Crystal Oscillator Table 9-1 Crystal Oscillator Circuit Parameters Symbol fOSC TOSC Rf Rd Cg Cd Min Typ 40 1/fOSC 1 100 10 10 Max Units MHz ns M k pF pF 2 3 18 20 S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 47 10 Registers 10.1 Register Set The S1D13700 registers are listed in the following table. Table 10-1: S1D13700 Register Set Register Pg LCD Register Descriptions (Offset = 8000h) System Control Registers REG[00h] Memory Configuration Register REG[02h] Vertical Character Size Register REG[04h] Total Character Bytes Per Row Register REG[06h] Horizontal Address Range Register 0 REG[08h] Power Save Mode Register 48 53 53 54 55 REG[01h] Horizontal Character Size Register REG[03h] Character Bytes Per Row Register REG[05h] Frame Height Register REG[07h] Horizontal Address Range Register 1 52 53 54 54 Register Pg Display Control Registers REG[09h] Display Enable Register REG[0Bh] Screen Block 1 Start Address Register 0 REG[0Dh] Screen Block 1 Size Register REG[0Fh] Screen Block 2 Start Address Register 1 REG[11h] Screen Block 3 Start Address Register 0 REG[13h] Screen Block 4 Start Address Register 0 REG[15h] Cursor Width Register REG[17h] Cursor Shift Direction Register REG[19h] Character Generator RAM Start Address Register 0 REG[1Bh] Horizontal Pixel Scroll Register 56 58 58 58 59 59 63 64 67 68 REG[0Ah] Display Attribute Register REG[0Ch] Screen Block 1 Start Address Register 1 REG[0Eh] Screen Block 2 Start Address Register 0 REG[10h] Screen Block 2 Size Register REG[12h] Screen Block 3 Start Address Register 1 REG[14h] Screen Block 4 Start Address Register 1 REG[16h] Cursor Height Register REG[18h] Overlay Register REG[1Ah] Character Generator RAM Start Address Register 1 56 58 58 59 59 59 63 65 67 Drawing Control Registers REG[1Ch] Cursor Write Register 0 REG[1Eh] Cursor Read Register 0 69 70 REG[1Dh] Cursor Write Register 1 REG[1Fh] Cursor Read Register 1 69 70 GrayScale Register REG[20h] Bit-Per-Pixel Select Register 71 Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 48 Epson Research and Development Vancouver Design Center 10.2 Register Restrictions All reserved bits must be set to 0 unless otherwise specified. Writing a value to a reserved bit may produce undefined results. Bits marked as n/a have no hardware effect. 10.3 Register Descriptions 10.3.1 System Control Registers The following registers initialize the S1D13700, set the window sizes, and select the LCD interface format. Incorrect configuration of these registers may cause other commands to operated incorrectly. For an example initialization of the S1D13700, see Section 15.1.2, "Initialization Example" on page 105. SYSTEM SET The SYSTEM SET command is used to initialize the S1D13700 and the display when indirect addressing is used. The values from REG[00h] through REG[07h] are passed as parameters when the SYSTEM SET command is issued. For further information on the SYSTEM SET command, see Section 11.1.1, "SYSTEM SET" on page 73. REG[00h] Memory Configuration Register Address = 8000h n/a 7 6 Screen Origin Compensation 5 Reserved 4 Panel Drive Select 3 Character Height 2 Reserved 1 Read/Write Character Generator Select 0 Note When REG[00h] is written to, the S1D13700 automatically performs the following functions. 1. Resets the internal timing generator 2. Disables the display 3. When indirect addressing mode is selected, completes and exits power save mode S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 49 bit 5 Screen Origin Compensation (IV) This bit controls Screen Origin Compensation which is used for inverse display and is usually set to 1. A common method of displaying inverted characters is to Exclusive-OR the text layer with the graphics back-ground layer. However when this is done, the inverted characters at the top or left of the screen become difficult to read. This is because the character origin is at the top-left of its bitmap and there are no background pixels either above or to the left of these characters. This bit causes the S1D13700 to offset the text screen against the graphics back layer by one vertical pixel. To shift the text screen horizontally, the horizontal pixel scroll function (REG[1Bh] or the HDOT SCR command for indirect addressing) can be used to shift the text screen 1 to 7 pixels to the right. If both of these functions are enabled, all characters have the appropriate surrounding back-ground pixels to ensure easy reading of the inverted characters. When this bit = 0, screen origin compensation is done. When this bit = 1, screen origin compensation is not done. The following figure shows an example of screen origin compensation and the HDOT SCR command in use. Display start point Back layer HDOT SCR (REG[1Bh]) Character REG[00h] bit 5 = 0 1 dot Dots 1 to 7 Figure 10-1 Screen Origin Compensation and HDOT SCR Adjustment bit 4 Reserved The default value for this bit is 1. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 50 Epson Research and Development Vancouver Design Center bit 3 Panel Drive Select (W/S) This bit specifies the LCD panel drive method. When this bit = 0, a single panel drive is selected. When this bit = 1, a dual panel drive is selected. The following diagrams show examples of the possible drive methods. XECL X driver X driver FPFRAME Y driver LCD Figure 10-2 Single Drive Panel Display XECL X driver X driver FPFRAME Upper Panel Y driver Lower Panel X driver X driver Figure 10-3 Dual Drive Panel Display The following table summarizes the parameters that must be configured for correct operation of an LCD panel. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 51 Table 10-2 LCD Parameter Summary Parameter C/R TC/R L/F SL1 SL2 SAD1 SAD2 SAD3 SAD4 Cursor movement range Single Panel (REG[00h] bit 3 = 0) REG[00h] bit 5 = 1 (IV) REG[03h] bits 7-0 REG[04h] bits 7-0 REG[05h] bits 7-0 00h to REG[05h] bits 7-0 00h to REG[05h] bits 7-0 REG[00h] bit 5 = 0 (IV) REG[03h] bits 7-0 REG[04h] bits 7-0 REG[05h] bits 7-0 Dual Panel (REG[00h] bit 3 = 1) REG[00h] bit 5 = 1 (IV) REG[03h] bits 7-0 REG[04h] bits 7-0 REG[05h] bits 7-0 REG[00h] bit 5 = 0 (IV) REG[03h] bits 7-0 REG[04h] bits 7-0 REG[05h] bits 7-0 00h to REG[05h] bits 7-0 [REG[05h] bits 7-0 + 1] / 2 - 1 [REG[05h] bits 7-0 + 1] / 2 - 1 (See Note) 00h to REG[05h] bits 7-0 [REG[05h] bits 7-0 + 1] / 2 - 1 [REG[05h] bits 7-0 + 1] / 2 - 1 (See Note) First screen block (Start Address = REG[0Bh], REG[0Ch]) Second screen block (Start Address = REG[0Eh], REG[0Fh]) Third screen block (Start Address = REG[11h], REG[12h]) Invalid Continuous movement over whole screen Fourth screen block (Start Address = REG[13h], REG[14h]) Above-and-below configuration: continuous movement over whole screen Note Screen Origin Compensation shifts the character font down by one pixel row. If the bottom pixel row of the font is at the bottom of the Screen Block, that row disappears when REG[00h] bit 5 = 0. To compensate for the bad visual effect, SL can be increased by one. bit 2 Character Height (M2) This bit selects the height of the character bitmaps. It is possible to display characters greater than 16 pixels high by creating a bitmap for each portion of each character and using graphics mode to reposition them. When this bit = 0, the character height is 8 pixels. When this bit = 1, the character height is 16 pixels. Reserved The default value for this bit is 0. Character Generator Select (M0) This bit determines whether characters are generated by the internal character generator ROM (CGROM) or character generator RAM (CGRAM). The CGROM contains 160, 5x7 pixel characters which are fixed at fabrication. The CGRAM can contain up to 256 user-defined characters which are mapped at the CG Start Address (REG[1Ah] REG[19h]). However, when the CGROM is used, the CGRAM can only contain up to 64, 8x8 pixel characters. When this bit = 0, the internal CGROM is selected. When this bit = 1, the internal CGRAM is selected. bit 1 bit 0 Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 52 Epson Research and Development Vancouver Design Center REG[01h] Horizontal Character Size Register Address = 8001h MOD 7 6 n/a 5 4 3 Horizontal Character Size bits 3-0 2 1 Read/Write 0 bit 7 MOD This bit selects the AC frame drive waveform period. MOD is typically set to 1. When this bit = 0, 16-line AC drive is selected. When this bit = 1, two-frame AC drive is selected. In two-frame AC drive, the MOD period is twice the frame period. In 16-line AC drive, MOD inverts every 16 lines. Although 16-line AC drive gives a more readable display, horizontal lines may appear when using high LCD drive voltages or at high viewing angles. bits 3-0 Horizontal Character Size (FX) bits [3:0] These bits define the horizontal size, or width, of each character, in pixels. REG[01h] bits 3-0 = Horizontal Character Size in pixels - 1 The S1D13700 handles display data in 8-bit units, therefore characters larger than 8 pixels wide must be formed from 8-pixel segments. The following diagram shows an example of a character requiring two 8-pixel segments where the remainder of the second eight bits are not displayed. This also applies to the second screen layer. In graphics mode, the normal character field is also eight pixels. If a wider character field is used, any remainder in the second eight bits is not displayed. FX FX FY 8 bits FY 8 bits 8 bits 8 bits Address A Address B Non-display area Where: FX = horizontal character size in pixels (REG[01h] bits 3-0) FY = vertical character size in pixels (REG[02h] bits 3-0) Figure 10-4 Horizontal and Vertical Character Size Example S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 53 REG[02h] Vertical Character Size Register Address = 8002h n/a 7 6 5 4 3 Vertical Character Size bits 3-0 2 1 Read/Write 0 bit 3-0 Vertical Character Size (FY) bits [3:0] These bits define the vertical size, or height, of each character, in pixels. REG[02h] bits 3-0 = Vertical Character Size in pixels - 1 REG[03h] Character Bytes Per Row Register Address = 8003h Character Bytes Per Row bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 Character Bytes Per Row (C/R) bits [7:0] These bits determine the size of each character row (or display line), in bytes, to a maximum of 239. The value of these bits is defined in terms of C/R which is calculated in Section 15.1.1, "SYSTEM SET Command and Parameters" on page 103. REG[03h] bits 7-0 = ([C/R] x bpp) - 1 REG[04h] Total Character Bytes Per Row Register Address = 8004h Total Character Bytes Per Row bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 Total Character Bytes Per Row (TC/R) bits [7:0] These bits set the length of one line, including horizontal blanking, in bytes, to a maximum of 255. The value of these bits is defined in terms of TC/R which is calculated in Section 15.1.1, "SYSTEM SET Command and Parameters" on page 103. TC/R can be adjusted to hold the frame period constant and minimize jitter for any given main oscillator frequency, fosc. REG[04h] bits 7-0 = [TC/R] + 1 Note TC/R must be programmed such that the following formulas are valid. [TC/R] [C/R] + 2 0 [TC/R] 255 Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 54 Epson Research and Development Vancouver Design Center REG[05h] Frame Height Register Address = 8005h Frame Height bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 Frame Height (L/F) bits [7:0] These bits determine the frame height, in lines. The maximum frame height is 256 lines. REG[05h] bits 7-0 = frame height in lines - 1. Note If the Panel Drive Select bit is set for a dual drive panel (REG[00h] bit 3 = 1), the frame height must be an even number of lines resulting in an odd number value for REG[05h] bits 7-0. REG[06h] Horizontal Address Range Register 0 Address = 8006h Horizontal Address Range bits 7-0 7 6 5 4 3 2 1 Read/Write 0 REG[07h] Horizontal Address Range Register 1 Address = 8007h Horizontal Address Range bits 15-8 7 6 5 4 3 2 1 Read/Write 0 bits 15-0 Horizontal Address Range (AP) bits [15:0] These bits define the horizontal address range of the virtual screen. The maximum value for this register is 7FFFh. REG[07h] bits 7-0, REG[06h] bits 7-0 = Addresses per line The following diagram demonstrates the relationship between the Horizontal Address Range and the Character Bytes Per Row value. Display area C/R Display memory limit Where: C/R = character bytes per row (REG[03h] bits 7-0) AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) AP Figure 10-5 Horizontal Address Range and Character Bytes Per Row Relationship S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 55 POWER SAVE The POWER SAVE command is used to enter standby mode on the S1D13700 when indirect addressing is used. For further information on the POWER SAVE command, see Section 11.1.2, "POWER SAVE" on page 73. REG[08h] Power Save Mode Register Address = 8008h n/a 7 6 5 4 3 2 1 Read/Write Power Save Mode Enable 0 bit 0 Power Save Mode Enable This bit controls the state of the software initiated power save mode. When power save mode is disabled, the S1D13700 is operating normally. When power save mode is enabled, the S1D13700 is in a power efficient state where all internal operations, including the oscillator, are stopped. For more information on the condition of the S1D13700 during Power Save Mode, see Section 17, "Power Save Mode" on page 126. When this bit = 0, power save mode is disabled (see note). When this bit = 1, power save mode is enabled (default). Note To fully disable power save mode when in Direct mode, a dummy write to any register must be performed after setting REG[08h] bit 0 = 0. To fully disable power save mode when in Indirect mode, at least two dummy writes to any register must be performed after setting REG[08h] bit 0 = 0. Note Enabling power save mode automatically clears the Display Enable bit (REG[09h] bit 0). After power save mode is disabled, the Display Enable bit must be set (REG[09h] bit 0 = 1) in order to turn on the display again. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 56 Epson Research and Development Vancouver Design Center 10.3.2 Display Control Registers These registers enable/disable the display, and control the cursor and layered screens. DISP ON/OFF The DISP ON/OFF command is used to enable/disable the display and display attributes when indirect addressing is used. The values from REG[0Ah] are passed as parameters when the DISP ON/OFF command is issued. For further information on the DISP ON/OFF command, see Section 11.1.3, "DISP ON/OFF" on page 74. REG[09h] Display Enable Register Address = 8009h n/a 7 6 5 4 3 2 1 Read/Write Display Enable 0 bit 0 Display Enable This bit controls the LCD display, including the cursor and all layered screens. The display enable bit takes precedence over the individual attribute bits in the Display Attribute register, REG[0Ah]. For information on LCD pin states when the display is off (REG[09h] bit 0 = 0), see Table 17-1 "State of LCD Pins During Power Save Mode," on page 126. When this bit = 0, the display is off. When this bit = 1, the display is on. REG[0Ah] Display Attribute Register Address = 800Ah SAD3 Attribute bits 1-0 7 6 SAD2 Attribute bits 1-0 5 4 SAD1 Attribute bits 1-0 3 2 1 Read/Write Cursor Attribute bits 1-0 0 bits 7-6 SAD3 Attribute (FP 5-4) bits [1:0] These bits control the attributes of the third screen block (SAD3) as follows. Table 10-3 Screen Block 3 Attribute Selection Third Screen Block (SAD3) REG[0Ah] bit 7 0 0 1 1 REG[0Ah] bit 6 0 1 0 1 ON Attributes OFF (Blank) No Flashing Flash at fFR/32 Hz (approx. 2 Hz) Flash at fFR/4 Hz (approx. 16 Hz) S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 57 bits 5-4 SAD2 Attribute (FP 3-2) bits [1:0] These bits control the attributes of the second screen block (SAD2). These bits also control the attributes of the fourth screen block (SAD4) when it is enabled by setting the Panel Drive Select bit to dual panel mode (REG[00h] bit 3 = 1). In this mode, the attributes of the second screen block (SAD2) and the fourth screen block (SAD4) share the same settings and cannot be set independently. Table 10-4 Screen Block 2/4 Attribute Selection Second Screen Block (SAD2, SAD4) REG[0Ah] bit 5 0 0 1 1 REG[0Ah] bit 4 0 1 0 1 ON Attributes OFF (Blank) No Flashing Flash at fFR/32 Hz (approx. 2 Hz) Flash at fFR/4 Hz (approx. 16 Hz) bits 3-2 SAD1 Attribute (FP 1-0) bits [1:0] These bits control the attributes of the first screen block (SAD1) as follows. Table 10-5 Screen Block Attribute Selection First Screen Block (SAD1) REG[0Ah] bit 3 0 0 1 1 REG[0Ah] bit 2 0 1 0 1 ON Attributes OFF (Blank) No Flashing Flash at fFR/32 Hz (approx. 2 Hz) Flash at fFR/4 Hz (approx. 16 Hz) bits 1-0 Cursor Attribute (FC) bits [1:0] These bits control the cursor and set the flash rate. The cursor flashes with a 70% duty cycle (ON 70% of the time and OFF 30% of the time). Table 10-6 Cursor Flash Rate Selection Bit 1 0 0 1 1 Bit 0 0 1 0 1 ON ON ON Cursor Display OFF (Blank) No Flashing Flash at fFR/32 Hz (approx. 2 Hz) Flash at fFR/64 Hz (approx. 1 Hz) Note When the cursor is disabled, a write to memory automatically enables the cursor and places the cursor at the next memory location. A read from memory does not enable the cursor, however, it still places the cursor at the next memory location. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 58 Epson Research and Development Vancouver Design Center SCROLL The SCROLL command is used to configure the display start addresses for the various screen blocks when indirect addressing is used. The values from REG[0Bh] through REG[14h] are passed as parameters when the SCROLL command is issued. For further information on the SCROLL command, see Section 11.1.4, "SCROLL" on page 75. REG[0Bh] Screen Block 1 Start Address Register 0 Address = 800Bh Screen Block 1 Start Address bits 7-0 (LSB) 7 6 5 4 3 2 1 0 Read/Write REG[0Ch] Screen Block 1 Start Address Register 1 Address = 800Ch Screen Block 1 Start Address bits 15-8 (MSB) 7 6 5 4 3 2 1 Read/Write 0 bits 15-0 Screen Block 1 Start Address (SAD1) bits [15:0] These bits determine the memory start address of screen block 1. REG[0Dh] Screen Block 1 Size Register Address = 800Dh Screen Block 1 Size bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 Screen Block 1 Size (SL1) bits [7:0] These bits determine the size of screen block 1, in lines. REG[0Dh] bits 7-0 = screen block 1 size in number of lines - 1 Note The relationship between the screen block start address (SADx), screen block size (SLx), and the display mode is described in Table 10-7 "Display Modes," on page 60. REG[0Eh] Screen Block 2 Start Address Register 0 Address = 800Eh Screen Block 2 Start Address bits 7-0 (LSB) 7 6 5 4 3 2 1 Read/Write 0 REG[0Fh] Screen Block 2 Start Address Register 1 Address = 800Fh Screen Block 2 Start Address bits 15-8 (MSB) 7 6 5 4 3 2 1 Read/Write 0 bits 15-0 Screen Block 2 Start Address (SAD2) bits [15:0] These bits determine the memory start address of screen block 2. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 59 REG[10h] Screen Block 2 Size Register Address = 8010h Screen Block 2 Size bits 7-0 7 6 5 4 3 2 1 Read/Write 0 bits 7-0 Screen Block 2 Size (SL2) bits [7:0] These bits determine the size of screen block 2, in lines. REG[10h] bits 7-0 = screen block 2 size in number of lines - 1 Note The relationship between the screen block start address (SADx), screen block size (SLx), and the display mode is described in Table 10-7 "Display Modes," on page 60. REG[11h] Screen Block 3 Start Address Register 0 Address = 8011h Screen Block 3 Start Address bits 7-0 (LSB) 7 6 5 4 3 2 1 Read/Write 0 REG[12h] Screen Block 3 Start Address Register 1 Address = 8012h Screen Block 3 Start Address bits 15-8 (MSB) 7 6 5 4 3 2 1 Read/Write 0 bits 15-0 Screen Block 3 Start Address (SAD3) bits [15:0] These bits determine the memory start address of screen block 3. REG[13h] Screen Block 4 Start Address Register 0 Address = 8013h Screen Block 4 Start Address bits 7-0 (LSB) 7 6 5 4 3 2 1 Read/Write 0 REG[14h] Screen Block 4 Start Address Register 1 Address = 8014h Screen Block 4 Start Address bits 15-8 (MSB) 7 6 5 4 3 2 1 Read/Write 0 bits 15-0 Screen Block 4 Start Address (SAD4) bits [15:0] These bits determine the memory start address of screen block 4. The following table summaries the required settings for each possible display mode. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 60 Epson Research and Development Vancouver Design Center Table 10-7 Display Modes REG[00h] bit 3 (W/S) Screen First Screen Block Second Screen Block First Layer SAD1 SL1 Second Layer SAD2 SL2 SAD3 (see note 1) Third Screen Block (partitioned screen) Set both SL1 and SL2 to L/F + 1 if not using a partitioned screen. Screen Configuration Example SAD2 SAD1 0 SL1 SAD3 Character or Graphics page 3 Character or Graphics page 1 SL2 Graphics display page 2 Layer 1 Layer 2 First Screen Block Second Screen Block SAD1, SL1 SAD3 (see note 2) SAD2, SL2 SAD4 (see note 2) Set both SL1 and SL2 to ([L/F] / 2 + 1) Screen Configuration Example SAD2 SAD1 1 SL1 SAD3 Character or Graphics display page 1 Graphics display page 2 Character or Graphics display page 3 Layer 1 Layer 2 Graphics display page 4 (SAD4) S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 61 Table 10-7 Display Modes (Continued) REG[00h] bit 3 (W/S) Screen First Screen Block Second Screen Block Set SL1 > SL2 Screen Configuration Example SAD2 SAD1 First Layer SAD1, SL1 -- Second Layer SAD2, SL2 SAD3 (see note 2) 0 SL1 Graphics display page 1 Graphics display page 2 Graphics display page 3 (SAD3) Layer 1 Layer 2 REG[00h] bit 3 (W/S) Screen Three-Layer Configuration First Layer SAD1, SL1 = L/F + 1 Second Layer SAD2, SL2 = L/F + 1 Third Layer SAD3 Screen Configuration Example SAD3 SAD2 SAD1 SL1 Graphics display page 1 Graphics display page 3 SL2 0 Graphics display page 2 Layer 1 Layer 3 Layer 2 Note 1 2 3 The size of screen block 3, in lines, is automatically set to the size of the screen block with the least number of lines (either SL1 or SL2). The parameters corresponding to SL3 and SL4 are fixed by REG[05h] bits 7-0 (L/F) and do not have to be set. If a dual panel is selected (REG[00h] bit 3 = 1), the differences between SL1 and (L/F + 1) / 2, and between SL2 and (L/F + 1) / 2, are blanked. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 62 Epson Research and Development Vancouver Design Center SL1 Upper Panel L/F L/F/2 Lower Panel Graphics Where: SL1 = screen block 1 size (REG[0Dh] bits 7-0) L/F = (REG[05h] bits 7-0) Figure 10-6 Dual Panel Display Height CSRFORM The CSRFORM command is used to configure the S1D13700 cursor when indirect addressing is used. The values from REG[15h] through REG[16h] are passed as parameters when the CSRFORM command is issued. For further information on the CSRFORM command, see Section 11.1.5, "CSRFORM" on page 76. The cursor registers are used to set the size, shape, and position of the cursor. Although the cursor is normally only used for text displays, it may be used for graphics displays when displaying special characters. Character origin 0 1 2 3 4 5 6 7 8 9 CRX = 5 pixels CRY = 9 lines CM = underscore (0) 0123456* * * Where: CRX = cursor width (REG[15h] bits 3-0) CRY = cursor height (REG[16h] bits 3-0) CM = cursor mode (REG[16h] bit 7) Figure 10-7 Cursor Size and Position S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 63 REG[15h] Cursor Width Register Address = 8015h n/a 7 6 5 4 3 Cursor Width bits 3-0 2 1 Read/Write 0 bits 3-0 Cursor Width (CRX) bits[3:0] These bits specify the width (or horizontal size) of the cursor, in pixels from the character origin (see Figure 10-7 "Cursor Size and Position," on page 62). REG[15h] bits 3-0 = cursor width in pixels - 1 Note The cursor width must be less than or equal to the horizontal character size. (REG[16h] bits 3-0 <= REG[01h] bits 3-0) REG[16h] Cursor Height Register Address = 8016h Cursor Mode 7 6 n/a 5 4 3 Cursor Height bits 3-0 2 1 Read/Write 0 bit 7 Cursor Mode (CM) This bit determines the cursor mode. When graphics mode is selected, this bit must be set to 1. When this bit = 0, an underscore cursor ( _ ) is selected. When this bit = 1, a block cursor ( ) is selected. Cursor Height (CRY) bits [3:0] For an underscore cursor (REG[16h] bit 7 = 0), these bits set the location of the cursor, in lines from the character origin (see Figure 10-7 "Cursor Size and Position," on page 62). For a block cursor (REG[16h] bit 7 = 1), these bits set the height (or vertical size) of the cursor, in lines from the character origin (see Figure 10-7 "Cursor Size and Position," on page 62). REG[16h] bits 3-0 = cursor height in lines - 1 Note bits 3-0 The vertical cursor size must be less than or equal to the vertical character size. (REG[16h] bits 3-0 <= REG[02h] bits 3-0) Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 64 Epson Research and Development Vancouver Design Center CSRDIR The CSRDIR command controls cursor movement when indirect addressing is used. The values from REG[17h] are passed as part of the command when the CSRDIR command is issued. For further information on the CSRDIR command, see Section 11.1.6, "CSRDIR" on page 76. REG[17h] Cursor Shift Direction Register Address = 8017h n/a 7 6 5 4 3 2 1 Read/Write Cursor Shift Direction bits 1-0 0 bits 1-0 Cursor Shift Direction bits [1:0] These bits set the direction of automatic cursor increment when the cursor is automatically moved after a memory access (read or write). The cursor can move left/right by one character or up/down by the number of bytes specified by the horizontal address range (or address pitch), REG[06h] - REG[07h]. When reading from and writing to display memory, this automatic cursor increment controls the display memory address increment on each read or write. 10 -AP -1 +1 01 00 +AP 11 AP = Horizontal Address Range (REG[06h] bits 7-0, REG[07h] bits 7-0) Figure 10-8 Cursor Direction Table 10-8 Cursor Shift Direction Direct Mode Bit 1 0 0 1 1 Bit 0 0 1 0 1 Indirect Mode Command 4C 4D 4E 4F Shift Direction Right Left Up Down Note The cursor moves in address units even if horizontal character size is equal to 9 (REG[01h] bits 3-0 = 9), therefore the cursor address increment must be preset for movement in character units. For further information, see Section 12.3, "Cursor Control" on page 86. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 65 OVLAY The OVLAY command selects layered screen composition and screen text/graphics mode when indirect addressing is used. The values from REG[18h] are passed as parameters when the OVLAY command is issued. For further information on the OVLAY command, see Section 11.1.7, "OVLAY" on page 77. REG[18h] Overlay Register Address = 8018h n/a 7 6 5 3 Layer Overlay Select 4 Screen Block 3 Display Mode 3 Screen Block 1 Display Mode 2 1 Read/Write Layer Composition Method bits 1-0 0 bit 4 3 Layer Overlay Select (OV) This bit determines how many layers are used when graphics mode is enabled. For mixed text and graphics, this bit must be set to 0. When this bit = 0, two layers are used. When this bit = 1, three layers are used. Screen Block 3 Display Mode (DM1) This bit determines the display mode for screen block 3. When this bit = 0, screen block 3 is configured for text mode. When this bit = 1, screen block 3 is configured for graphics mode. Note bit 3 Screen blocks 2 and 4 can display graphics only. bit 2 Screen Block 1 Display Mode (DM0) This bit determines the display mode for screen block 1. When this bit = 0, screen block 1 is configured for text mode. When this bit = 1, screen block 1 is configured for graphics mode. Note Screen blocks 2 and 4 can display graphics only. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 66 Epson Research and Development Vancouver Design Center bits 1-0 Layer Composition Method (MX) bits [1:0] These bits select the layered screen composition method, which can be OR, AND, or Exclusive-OR. Since the screen composition is organized in layers and not by screen blocks, when using a layer divided into two screen blocks, different composition methods cannot be specified for the individual screen blocks. Table 10-9 Composition Method Selection REG[18h] bit 1 REG[18h] bit 0 0 0 1 1 0 1 0 1 Function L1 L2 L3 (L1 L2) L3 (L1 L2) L3 Composition Method OR Exclusive-OR AND Applications Underlining, rules, mixed text and graphics Inverted characters, flashing regions, underlining Simple animation, three-dimensional appearance Reserved Note L1: First layer (text or graphics). If text is selected, layer L3 cannot be used. L2: Second layer (graphics only) L3: Third layer (graphics only) Layer 1 1 Layer 2 Layer 3 Visible display EPSON EPSON OR 2 EPSON EPSON Exclusive OR 3 EPSON SON AND Figure 10-9 Combined Layer Display Examples Note L1: Not flashing L2: Flashing at 1 Hz L3: Flashing at 2 Hz S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 67 CGRAM ADR The CGRAM ADR command sets the start address of the character generator RAM (CGRAM) when indirect addressing is used. The values from REG[19h] through REG[1Ah] are passed as parameters when the CGRAM ADR command is issued. For further information on the CGRAM ADR command, see Section 11.1.8, "CGRAM ADR" on page 77. REG[19h] Character Generator RAM Start Address Register 0 Address = 8019h CGRAM Start Address bits 7-0 (LSB) 7 6 5 4 3 2 1 0 Read/Write REG[1Ah] Character Generator RAM Start Address Register 1 Address = 801Ah CGRAM Start Address bits 15-8 (MSB) 7 6 5 4 3 2 1 Read/Write 0 bits 15-0 Character Generator RAM Start Address bits [15:0] These bits determine the memory start address of the Character Generator RAM (CGRAM). The exact memory location of the start of each character stored in CGRAM can be calculated by multiplying the character code index by the character height and adding the total to the CGRAM start address. For example, to determine the address of a 8x8 character at character code index 80h with a CGRAM start address of 6000h, the following calculation can be used. character start = (character code index x character height) + CGRAM start address = (80h x 8) + 6000h = 400h + 6000h = 6400h The character starts in RAM at address 6400h and takes 8 memory locations. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 68 Epson Research and Development Vancouver Design Center HDOT SCR The HDOT SCR command sets the horizontal scroll position when indirect addressing is used. The values from REG[1Bh] are passed as parameters when the HDOT SCR command is issued. For further information on the HDOT SCR command, see Section 11.1.9, "HDOT SCR" on page 77. Normal scrolling on text screens allows scrolling of entire characters only. The HDOT SCR command provides horizontal pixel scrolling for text screens. HDOT SCR cannot be used on individual layers. Note HDOT SCR must be set to zero for all display modes except 1 bpp (REG[20h] Bit-PerPixel Select Register bits 1-0 = 0). REG[1Bh] Horizontal Pixel Scroll Register Address = 801Bh n/a 7 6 5 4 3 2 1 Read/Write Horizontal Pixel Scroll bits 2-0 0 bits 2-0 Horizontal Pixel Scroll bits [2:0] These bits specify the number of horizontal pixels to scroll the display. The character bytes per row (C/R), REG[03h] bits 7-0, must be set to one more than the actual number of horizontal characters before using horizontal pixel scroll. Smooth scrolling can be simulated by repeatedly changing the value of REG[1Bh] bits 2-0. See Section 12.5, "Scrolling" on page 92 for more information on scrolling the display. M A B X Y M=0 N=0 Y Z A B X Y Z A B Display width X N M/N is the number of bits (dots) that parameter 1 (P1) is incremented/decremented by. Figure 10-10 Horizontal Scrolling S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 69 10.3.3 Drawing Control Registers CSRW The CSRW command sets the cursor address when indirect addressing is used. The values from REG[1Ch] through REG[1Dh] are passed as parameters when the CSRW command is issued. For further information on the CSRW command, see Section 11.1.10, "CSRW" on page 78. REG[1Ch] Cursor Write Register 0 Address = 801Ch Cursor Write bits 7-0 (LSB) 7 6 5 4 3 2 1 0 Write Only REG[1Dh] Cursor Write Register 1 Address = 801Dh Cursor Write bits 15-8 (MSB) 7 6 5 4 3 2 1 Write Only 0 bits 15-0 Cursor Write (CSRW) bits [15:0] These bits set the display memory address to the data at the cursor position as shown in Figure 12-10 "Cursor Movement," on page 88. Note The microprocessor cannot directly access the display memory in indirect addressing mode. For Indirect Addressing Mode: The MREAD and MWRITE commands use the address in this register when in indirect mode. The cursor address register can only be modified by the CSRW command, and by the automatic increment after an MREAD or MWRITE command. It is not affected by display scrolling. If a new address is not set, display memory accesses are from the last set address or the address after previous automatic increments. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 70 Epson Research and Development Vancouver Design Center CSRR The CSRR command reads the cursor address when indirect addressing is used. The values from REG[1Eh] through REG[1Fh] are passed as parameters when the CSRR command is issued. For further information on the CSRR command, see Section 11.1.11, "CSRR" on page 78. REG[1Eh] Cursor Read Register 0 Address = 801Eh Cursor Read bits 7-0 (LSB) 7 6 5 4 3 2 1 0 Read Only REG[1Fh] Cursor Read Register 1 Address = 801Fh Cursor Read bits 15-8 (MSB) 7 6 5 4 3 2 1 Read Only 0 bits 15-0 Cursor Read (CSRR) bits [15:0] These bits are only used in Indirect Addressing mode. These bits indicate the memory address where the cursor is currently located. After issuing the command, the data read address is read twice. Once for the low byte and then again for the high byte of the register. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 71 10.3.4 Gray Scale Register GRAYSCALE The GRAYSCALE command selects the gray scale depth, in bits-per-pixel (bpp), when indirect addressing is used. The values from REG[20h] are passed as parameters when the GRAYSCALE command is issued. For further information on the GRAYSCALE command, see Section 11.1.12, "GRAYSCALE" on page 78. REG[20h] Bit-Per-Pixel Select Register Address = 8020h n/a 7 6 5 4 3 2 1 Read/Write Bit-Per-Pixel Select bits 1-0 0 bits 1-0 Bit-Per-Pixel Select bits [1:0] These bits select the bit-per-pixel mode as follows. Table 10-10 Bit-Per-Pixel Selection REG[20h] bits 1-0 00 01 10 11 Bits-Per-Pixel 1 2 4 Reserved Note The horizontal character size (REG[01h] bits 3-0) must be set to 7h and the Horizontal Pixel Scroll bits (REG[1Bh] bits 2-0) must be set to 0. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 72 Epson Research and Development Vancouver Design Center 11 Indirect Addressing Table 11-1 Indirect Addressing Command Set Class System Control Register Address 8000h - 8007h 8008h 8009h - 800A 800Bh - 8014h Display Control 8015h - 8016h 8017h 8018h 8019h - 801Ah 801Bh Drawing Control 801Ch - 801Dh 801Eh - 801Fh 8020h Memory Control Command Register Description Control Byte No. of Bytes Value 40h 53h 58h 59h 44h 5Dh 4Ch - 4Fh 5Bh 5Ch 5A 46h 47h 60h 42h 43h 8 0 1 10 2 0 1 2 1 2 2 1 n/a SYSTEM SET Initializes device and display POWER SAVE Enters standby mode Enables/disables display and display DISP ON/OFF attributes SCROLL CSRFORM CSRDIR OVLAY CGRAM ADR HDOT SCR CSRW CSRR GRAYSCALE MEMWRITE MEMREAD Sets screen block start addresses and sizes Sets cursor type Sets direction of cursor movement Sets display overlay format Sets start address of character generator RAM Sets horizontal scroll position Sets cursor address Reads cursor address Sets the Grayscale depth (bpp) Writes to memory Reads from memory Table 11-2 Generic Indirect Addressing Command/Write/Read A0 1 1 0 WR 0 1 0 RD 1 0 1 Command [C] Parameter Read [P#] Parameter Write [P#] Table 11-3 M6800 Indirect Addressing Command/Write/Read A0 1 1 0 R/W 0 1 0 E 1 1 1 Command write Display data and cursor address read Display data and parameter write Table 11-4 M68K Indirect Addressing Command/Write/Read A0 1 1 0 R/W LDS# 0 1 0 0 0 0 Command write Display data and cursor address read Display data and parameter write S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 73 11.1 System Control See Section 15.1.2, "Initialization Example" on page 105 for the initialization sequence. 11.1.1 SYSTEM SET See Section , "SYSTEM SET" on page 48 for further information. Table 11-5 SYSTEM SET Command and Parameters MSB LSB bit 7 0 0 MOD5 0 bit 6 1 0 0 0 bit 5 0 IV1 0 0 bit 4 0 0 0 0 bit 3 0 W/S2 bit 2 0 M23 bit 1 0 0 bit 0 0 M04 Indirect C P1 P2 P3 P4 P5 P6 P7 P8 REG[01h] bits 3-0 REG[02h] bits 3-0 REG[03h] bits 7-0 REG[04h] bits 7-0 REG[05h] bits 7-0 REG[06h] bits 7-0 REG[07h] bits 7-0 Note 1 2 3 4 5 IV is the Screen Origin Compensation bit, REG[00h] bit 5. W/S is the Panel Drive Select bit, REG[00h] bit 3. M2 is the Character Height bit, REG[00h] bit 2. M0 is the Character Generator Select bit, REG[00h] bit 0. MOD is defined by REG[01h] bit 7. 11.1.2 POWER SAVE See Section , "POWER SAVE" on page 55 for further information. Table 11-6 POWER SAVE Command MSB LSB bit 7 0 bit 6 1 bit 5 0 bit 4 1 bit 3 0 bit 2 0 bit 1 1 bit 0 1 Indirect C Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 74 Epson Research and Development Vancouver Design Center 11.1.3 DISP ON/OFF The following parameters are used for the DISP ON command. For further details, see Section , "DISP ON/OFF" on page 56. Table 11-7 DISP ON Command and Parameters MSB LSB bit 7 0 bit 6 1 bit 5 0 bit 4 1 bit 3 1 bit 2 0 bit 1 0 bit 0 1 Indirect C P1 REG[0Ah] bits 7-0 The following parameters are used for the DISP OFF command. For further details, see Section , "DISP ON/OFF" on page 56. Table 11-8 DISP OFF Command and Parameters MSB LSB bit 7 0 bit 6 1 bit 5 0 bit 4 1 bit 3 1 bit 2 0 bit 1 0 bit 0 0 Indirect C P1 REG[0Ah] bits 7-0 S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 75 11.1.4 SCROLL See "SCROLL" on page 58 for further information. Table 11-9 SCROLL Command and Parameters MSB LSB bit 7 0 A7 A15 L7 A7 A15 L7 A7 A15 A7 A15 bit 6 1 A6 A14 L6 A6 A14 L6 A6 A14 A6 A14 bit 5 0 A5 A13 L5 A5 A13 L5 A5 A13 A5 A13 bit 4 0 A4 A12 L4 A4 A12 L4 A4 A12 A4 A12 bit 3 0 A3 A11 L3 A3 A11 L3 A3 A11 A3 A11 bit 2 1 A2 A10 L2 A2 A10 L2 A2 A10 A2 A10 bit 1 0 A1 A9 L1 A1 A9 L1 A1 A9 A1 A9 bit 0 0 A0 A8 L0 A0 A8 L0 A0 A8 A0 A8 REG[0Bh] bits 7-0 REG[0Ch] bits 7-0 REG[0Dh] bits 7-0 REG[0Eh] bits 7-0 REG[0Fh] bits 7-0 REG[10h] bits 7-0 REG[11h] bits 7-0 REG[12h] bits 7-0 REG[13h] bits 7-0 REG[14h] bits 7-0 Indirect C P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Note Set parameters P9 and P10 only if both dual panel (REG[00h] bit 3 = 1) and two-layer configuration are selected. SAD4 is the fourth screen block display start address. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 76 Epson Research and Development Vancouver Design Center 11.1.5 CSRFORM See "CSRFORM" on page 62 for further information. Table 11-10 CSRFORM Command and Parameters MSB LSB bit 7 0 0 CM1 bit 6 1 0 bit 5 0 0 bit 4 1 0 bit 3 1 bit 2 1 bit 1 0 bit 0 1 Indirect C P1 REG[15h] bits 3-0 X3 X2 X1 X0 0 0 0 REG[16h] bits 3-0 Y3 Y2 Y1 Y0 P2 Note 1 CM is the Cursor Mode bit, REG[16h] bit 7. 11.1.6 CSRDIR See "CSRDIR" on page 64 for further information. Table 11-11 CSRDIR Command MSB LSB bit 7 0 bit 6 1 bit 5 0 bit 4 0 bit 3 1 bit 2 1 bit 1 CD1 bit 0 CD0 Indirect C REG[17h] bits 1-0 S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 77 11.1.7 OVLAY See "OVLAY" on page 65 for further information. Table 11-12 OVLAY Command and Parameters MSB LSB bit 7 0 0 bit 6 1 0 bit 5 0 0 bit 4 1 OV1 bit 3 1 bit 2 0 bit 1 1 MX13 bit 0 1 MX03 Indirect C P1 DM22 DM12 Note 1 2 3 OV is the 3 Layer Overlay Select bit, REG[18h] bit 4. DM2 and DM1 are the Screen Block 3/1 Display Mode bits, REG[18h] bits 3-2. MX1 and MX0 are the Layer Composition Method bits, REG[18h] bits 1-0. 11.1.8 CGRAM ADR See "CGRAM ADR" on page 67 for further information. Table 11-13 CGRAM ADR Command and Parameters MSB LSB bit 7 0 A7 A15 bit 6 1 A6 A14 bit 5 0 A5 A13 bit 4 1 A4 A12 bit 3 1 A3 A11 bit 2 1 A2 A10 bit 1 0 A1 A9 bit 0 0 A0 A8 (SAGL) (SAGH) Indirect C P1 P2 11.1.9 HDOT SCR See "HDOT SCR" on page 68 for further information. Table 11-14 HDOT SCR Command and Parameters MSB LSB bit 7 0 0 bit 6 1 0 bit 5 0 0 bit 4 1 0 bit 3 1 0 bit 2 0 D2 bit 1 1 D1 bit 0 0 D0 Indirect C P1 Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 78 Epson Research and Development Vancouver Design Center 11.1.10 CSRW See "CSRW" on page 69 for further information. Table 11-15 CSRW Command and Parameters MSB LSB bit 7 0 A7 A15 bit 6 1 A6 A14 bit 5 0 A5 A13 bit 4 0 A4 A12 bit 3 0 A3 A11 bit 2 1 A2 A10 bit 1 1 A1 A9 bit 0 0 A0 A8 (CSRL) (CSRH) Indirect C P1 P2 11.1.11 CSRR See "CSRR" on page 70 for further information. Table 11-16 CSRR Command and Parameters MSB LSB bit 7 0 A7 A15 bit 6 1 A6 A14 bit 5 0 A5 A13 bit 4 0 A4 A12 bit 3 0 A3 A11 bit 2 1 A2 A10 bit 1 1 A1 A9 bit 0 1 A0 A8 (CSRL) (CSRH) Indirect C P1 P2 11.1.12 GRAYSCALE See Section , "GRAYSCALE" on page 71 for further information. Table 11-17 Gray Scale Command and Parameters MSB LSB bit 7 0 0 bit 6 1 0 bit 5 1 0 bit 4 0 0 bit 3 01 0 bit 2 0 0 bit 1 0 bit 0 0 Indirect C P1 BPP1 BPP0 11.1.13 Memory Control See "Drawing Control Registers" on page 69 for further information. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 79 12 Display Control Functions 12.1 Character Configuration The origin of each character bitmap is the top left corner as shown in Figure 12-1. Adjacent bits in each byte are horizontally adjacent in the corresponding character image. Although the size of the bitmap is fixed by the character generator, the actual displayed size of the character field can be varied in both dimensions. Character starting point FX R0 R1 R2 Character height R3 R4 R5 R6 D7 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 to 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Space data D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Space data FY R7 R8 R9 R10 Space R11 R12 R13 R14 R15 Character width Space Where: FX = horizontal character size is 16 pixels (REG[01h] bits 3-0) FY = vertical character size is 16 pixels (REG[02h] bits 3-0) Figure 12-1 Example of Character Display from Generator Bitmap (when [FX] 8) If the area outside the character bitmap contains only zeros, the displayed character size can be increased by increasing the horizontal character size (REG[01h] bits 3-0) and the vertical character size (REG[01h] bits 3-0). The zeros ensure that the extra space between displayed characters is blank. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 80 Epson Research and Development Vancouver Design Center The displayed character width can be set to any value up to 16 even if each horizontal row of the bitmap is two bytes wide. Horizontal non-display area FX Character Height FY 16 dots Space Vertical non-display area 8 dots 8 dots Character width Space Where: FX = horizontal character size is 16 pixels (REG[01h] bits 3-0) FY = vertical character size is 16 pixels (REG[02h] bits 3-0) Figure 12-2 Character Width Greater than One Byte Wide ([FX] = 9) Note The S1D13700 does not automatically insert spaces between characters. If the displayed character size is 8 pixels or less and the space between character origins is nine pixels or more, the bitmap must use two bytes per row, even though the character image requires only one. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 81 12.2 Screen Configuration 12.2.1 Screen Configuration The S1D13700 can be configured for a single text screen, overlapping text screens, or overlapping graphics screens. Graphics screens use eight times as much display memory as a text screen in 1 bpp. Figure 12-3 shows the relationship between the virtual screens and the physical screen. REG[0 3h] REG[0 6h], REG[0 7h] 0000h Character memory area 0800h 07FFh Graphics memory area Display Memory Window 47FFh (0,YM) (XW,YM) Y (0,0) (X,Y) (XM,YM) X (XM,0) Figure 12-3 Virtual and Physical Screen Relationship Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 82 Epson Research and Development Vancouver Design Center 12.2.2 Display Address Scanning The S1D13700 scans the display memory in the same way as a raster scan CRT screen. Each row is scanned from left to right until the address range equals C/R, REG[03h] bits 70. Rows are scanned from top to bottom. When in graphics mode, at the start of each line the address counter is set to the address at the start of the previous line plus the horizontal address range (or address pitch), REG[06h] - REG[07h]. In text mode, the address counter is set to the same start address, and the same character data is read, for each row in the character bitmap. However, a new row of the character generator output is used each time. Once all the rows in the character bitmap have been displayed, the address counter is set to the start address plus the horizontal address range (or address pitch) and the next line of text is displayed. 1 * * * 8 9 * * * 16 17 * * * 24 * * * * SAD SAD + 1 SAD + 2 SAD + C/R SAD + AP SAD + AP +1 SAD + AP +2 SAD + AP + C/R SAD + 2AP C/R Where: SAD = start address of the screen block AP = horizontal address range (REG[06h], REG[07h]) C/R = number of character bytes per row (REG[03h]) Note Assumes REG[00h] bit 3 = 0, REG[01h] bits 3-0 = 8, REG[02h] bits 3-0 = 8 Figure 12-4 Display Addressing in Text Mode Example Note One byte of display memory corresponds to one character. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 83 1 2 3 * * * * * * * * SAD SAD + AP SAD + 2AP SAD +1 SAD + AP +1 SAD + 2 SAD + AP +2 SAD + C/R SAD + AP + C/R Line 1 SAD SAD +1 SAD + 2 AP SAD + C/R SAD + AP SAD + AP + 1 AP SAD + AP + C/R SAD + 2AP Line 3 Line 2 REG[03h] bits 7-0 Where: SAD = start address of the screen block AP = horizontal address range (REG[06h], REG[07h]) C/R = number of character bytes per row (REG[03h]) Note Assumes REG[00h] bit 3 = 0, REG[01h] bits 3-0 = 8 Figure 12-5 Display Addressing in Graphics Mode Example Note In 1 bpp, one bit of display memory corresponds to one pixel. Therefore, 1 byte of display memory corresponds to 8 pixels. In 2 bpp, 1 byte corresponds to 4 pixels. In 4 bpp, 1 byte corresponds to 2 pixels. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 84 Epson Research and Development Vancouver Design Center 1a * * * 8a 9a * * * 16a 17a * * * 24a 25a * * * (L/F)/2 = 1b * * * 8b 9b * * * 16b 17b * * * 24b 25b * * * * (L/F) SAD1 SAD1 + 1 SAD1 + 2 SAD1 + C/R SAD1 + AP SAD1 + AP +1 SAD1 + AP +2 SAD1 + AP + C/R SAD1 + 2AP SAD3 + 1 SAD3 + 2 SAD3 + C/R SAD3 + AP SAD3 + AP +1 SAD3 + AP +2 SAD3 + AP + C/R SAD3 + 2AP C/R Where: SAD = start address of the screen block AP = horizontal address range (REG[06h], REG[07h]) C/R = number of character bytes per row (REG[03h]) L/F = frame height in lines (REG[05h]) Note Assumes REG[00h] bit 3 = 0, REG[01h] bits 3-0 = 8, REG[02h] bits 3-0 = 8 Figure 12-6 Dual Panel Display Address Indexing in Text Mode Note In dual panel drive, the S1D13700 reads line 1a and line 1b as one cycle. The upper and lower panels are thus read alternately, one line at a time. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 85 12.2.3 Display Scan Timing During display scanning, the S1D13700 pauses at the end of each line for TC/R - C/R ((REG[04h] bits 7-0) - (REG[03h] bits 7-0)) display memory read cycles, although the LCD drive signals are still generated. TC/R may be set to any value within the constraints imposed by C/R, Input Clock (CLK), fFR, and the size of the LCD panel. This pause may be used to fine tune the frame frequency. Alternately, the microprocessor may use this pause to access the display memory data. Display period TC/R C/R Line 1 2 Frame period 3 Divider frequency period O O O R R R L/F FPLINE * * * * * O R Where: C/R = character bytes per row (REG[03h] bits 7-0) TC/R = total character bytes per row (REG[04h] bits 7-0) L/F = frame height in lines (REG[05h] bits 7-0) Figure 12-7 Relationship Between Total Character Bytes Per Row and Character Bytes Per Row Note The divider adjustment interval (R) applies to both the upper and lower screens even if a dual panel drive is selected, REG[00h] bit 3 = 1. In this case, FPLINE is active only at the end of the lower screen's display interval. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 86 Epson Research and Development Vancouver Design Center 12.3 Cursor Control 12.3.1 Cursor Write Register Function The Cursor Write register (REG[1Ch] - REG[1Dh]) functions as both the displayed cursor position address register and, in indirect addressing mode, the display memory access address register. When accessing display memory outside the actual visible screen memory, the Cursor Write register should be saved before accessing the memory and then restored after the memory access is complete. This is done to prevent the cursor from visibly disappearing outside the display area. Cursor display address register REG[1Ch], REG[1Dh] Address pointer Figure 12-8 Cursor Addressing Note The cursor may disappear from the display if the cursor address remains outside the displayed screen memory for more than a few hundred milliseconds. 12.3.2 Cursor Movement On each memory access, the Cursor Write register (REG[1Ch] - REG[1Dh]) is changed by the amount specified by the CSRDIR command (see REG[17h] bits 1-0) which automatically moves the cursor to the desired location. 12.3.3 Cursor Display Layers Although the S1D13700 can display up to three layers, the cursor is displayed in only one of these layers. For a two layer configuration (REG[18h] bit 4 = 0), the cursor is displayed in the first layer (L1). For a three layer configuration (REG[18h] bit 4 = 1), the cursor is displayed in the third layer (L3). The cursor is not displayed if the address is moved outside of the memory for its layer. If it is necessary to display the cursor in a layer other than the present one, the layers may be swapped, or the cursor layer can be moved within the display memory. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 87 Although the cursor is normally displayed for character data, the S1D13700 may also display a dummy cursor for graphical characters. This is only possible if a graphics screen is displayed, the text screen is turned off, and the microprocessor generates the cursor control address. D (REG[09h] bit 0) = 1 FC1 (REG[0Ah] bit 1) = 0 FC0 (REG[0Ah] bit 0) = 1 Cursor ON FP1 (REG[0Ah] bit 3) = 0 FP0 (REG[0Ah] bit 2) = 0 Screen Block 1 Off (text screen) FP3 (REG[0Ah] bit 5) = 0 FP2 (REG[0Ah] bit 4) = 1 Screen Block 2 On (graphics screen) Figure 12-9 Cursor Display Layers For example, if Chinese characters are displayed on a graphics screen, the cursor address is set to the second screen block in order to write the "graphics" display data. However, the cursor is not displayed. To display the cursor, the cursor address must be set to an address within the blank text screen block. Since the automatic cursor increment is in address units, not character units, the controlling microprocessor must set the Cursor Write register (REG[1Ch] - REG[1Dh]) when moving the cursor over the graphical characters. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 88 Epson Research and Development Vancouver Design Center 8 dots 8 dots 8 dots 8 dots Block cursor 18 dots Auto shift Auto shift Auto shift Cursor address preset Figure 12-10 Cursor Movement If no text screen is displayed, only a bar cursor can be displayed at the cursor address. If the first layer is a mixed text and graphics screen and the cursor shape is set to a block cursor, the S1D13700 automatically decides which cursor shape to display. On the text screen it displays a block cursor, and on the graphics screen, a bar cursor. 12.4 Memory to Display Relationship The S1D13700 supports virtual screens that are larger than the physical size of the LCD panel address range (C/R), REG[03h] bits 7-0. A layer of the S1D13700 can be considered as a window into the larger virtual screen held in display memory. This window can be divided into two blocks, with each block able to display a different portion of the virtual screen. For example, this allows one block to dynamically scroll through a data area while the other block is used as a status message display area. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 89 For examples of the memory to display relationships, see Figure 12-11 "Screen Layers and Memory Relationship," on page 89 and Figure 12-12 "Virtual Display (Display Window to Memory Relationship)," on page 90, and Figure 12-13 "Memory Map and Magnified Characters," on page 91. AP REG[00h] bit 3 = 0 SAD1 SAD3 Display page 1 SAD2 Layer 1 Display page 2 Layer 2 SAD1 SAD1 SAD3 Display page 1 Display page 3 Layer 1 Display page 2 Layer 2 SAD3 C/R Graphics page 3 SAD2 Graphics page 2 C/R SAD3 Character page 3 C/R C/R Character page 1 SAD4 Graphics page 2 Graphics page 2 C/R CGRAM SAD2 SAD4 C/R Character page 1 Character page 3 SAD1 SAD3 REG[00h] bit 3 = 1 Display page 1 Display page 3 Layer 1 Display page 2 Display page 4 Layer 2 SAD2 SAD3 SAD2 Display page 3 SAD1 Display page 2 Display page 1 C/R SAD2 Graphics page 2 C/R SAD1 Graphics page 1 Layer 1 Layer 2 Layer 3 Where: SADx = start address of screen block x AP = horizontal address range (REG[06h], REG[07h]) C/R = number of character bytes per row (REG[03h]) Figure 12-11 Screen Layers and Memory Relationship Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 90 Epson Research and Development Vancouver Design Center AP 0000h SAD1 FX FY CRY CSRA L/F CRX Display window Virtual display memory limit C/R FFFFh Where: FX = horizontal character size is 16 pixels (REG[01h] bits 3-0) FY = vertical character size is 16 pixels (REG[02h] bits 3-0) CRX = cursor width is 16 pixels (REG[15h] bits 3-0) CRY = cursor height is 16 pixels (REG[16h] bits 3-0) C/R = character bytes per row is 240 bytes (REG[03h] bits 7-0) L/F = frame height is 256 (REG[05h] bits 7-0) AP = horizontal address range (or address pitch) is 64K bytes (REG[06h] bits 7-0, REG[07h] bits 7-0) Figure 12-12 Virtual Display (Display Window to Memory Relationship) S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 91 SAD1 D7 0000 SL1 0300 0400 to Page 1 D0 D7 to D0 0000 ABC A (Code) B C Character code Page 2 0800 SAD2 SL2 2000 Back layer 2800 0080 (MSB) D7 (LSB)(MSB) D0 D7 X Page 1 Y 02FF Display XY Page 2 SAG 4440 4800 CG RAM 4A00 Not used 802F 8030 Internal ROM 70h 88h 88h 88h F8h 88h 88h 00h D7 D0 #4800 1 2 3 4 5 6 #4807 1FFF (LSB) D0 01110000 10001000 10001000 10001000 11111000 10001000 10001000 00000000 Magnified image Example of character A Figure 12-13 Memory Map and Magnified Characters Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 92 Epson Research and Development Vancouver Design Center 12.5 Scrolling The microprocessor can control S1D13700 scrolling modes by writing the scroll address registers for each screen block, REG[0Bh] - REG[14h]. This is referred to as address scrolling and can be used for both text and graphic screen blocks, if the display memory capacity is greater than one screen. 12.5.1 On-Page Scrolling The normal method of scrolling within a page is to move the whole display up one line and erase the bottom line. However, the S1D13700 does not automatically erase the bottom line, so it must be erased with blanking data when changing the scroll address register. Display memory AP Before scrolling ABC WXYZ 789 SAD1 ABC WXYZ 789 C/R After scrolling WXYZ 789 SAD3 SAD1 WXYZ 789 Blank Blank Where: SADx = start address of screen block x AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) Figure 12-14 On-Page Scrolling S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 93 12.5.2 Inter-Page Scrolling Scrolling between pages and page switching can be performed only if the display memory capacity is greater than one screen. To scroll down one line/character, add the value of the horizontal address range (or address pitch), REG[06h] - REG[07h], to the current SADx. To scroll up, subtract the value of the horizontal address range from SADx. Display memory AP C/R ABC 789 SAD1 WXYZ 789 Before scrolling ABC WXYZ After scrolling WXYZ 789 SAD1 ABC WXYZ 789 Where: SADx = start address of screen block x AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) Figure 12-15 Inter-Page Scrolling Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 94 Epson Research and Development Vancouver Design Center 12.5.3 Horizontal Wraparound Scrolling For screen block in text mode, the display can be scrolled horizontally in one character units, regardless of the display memory capacity. Display Before scrolling ABC 123 XYZ SAD1 Display memory ABC 123 XYZ AP C/R After scrolling BC 23 XYZ1 SAD1 ABC 123 XYZ Where: SADx = start address of screen block x AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) Figure 12-16 Horizontal Wraparound Scrolling S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 95 12.5.4 Bi-directional Scrolling Bi-directional scrolling can be performed only if the display memory is larger than the physical screen in both the horizontal (REG[06h], REG[07h] > REG[03h]) and vertical directions. Scrolling is normally done in single-character units, however the HDOT SCR command (see REG[1Bh] bits 2-0) allows horizontal scrolling in pixel units (for text blocks only). Single pixel horizontal scrolling can be performed using both the SCROLL and HDOT SCR commands. For more information, see Section 15.3, "Smooth Horizontal Scrolling" on page 116. Note In 2 bpp and 4 bpp grayscale mode REG[1Bh] bits 2-0 (HDOT SCR) must be set to 0, so horizontal scrolling can only be done in single character units (not pixel units). Display memory Before scrolling BC EFG TUV AP 12 A BC EFG TUV C/R 12 34 567 89 After scrolling FG TUV 1234 56 ABC E FG TUV 1234 56 7 89 Where: AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) Figure 12-17 Bi-Directional Scrolling Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 96 Epson Research and Development Vancouver Design Center 12.5.5 Scroll Units The following table summarizes the units, or steps, that can be scrolled for each mode. Table 12-1 Scrolling Unit Summary Mode Text Graphics Vertical Characters Pixels Horizontal Pixels or Characters Pixels Note In a divided screen, each block cannot be independently scrolled horizontally in pixel units. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 97 13 Character Generator 13.1 CG Characteristics 13.1.1 Internal Character Generator The internal character generator is recommended for minimum system configurations containing a S1D13700, display RAM, LCD panel, single-chip microprocessor and power supply. Since the internal character generator uses a CMOS mask ROM, it is also recommended for low-power applications. * 5 x 7 pixel font (See Section 16, "Internal Character Generator Font" on page 125) * 160 JIS standard characters * Can be mixed with character generator RAM (maximum of 64 CGRAM characters) * Can be automatically spaced out up to 8 x 16 pixels 13.1.2 Character Generator RAM The character generator RAM can be used for storing graphics characters. The character generator RAM can be mapped to any display memory location by the microprocessor, allowing effective usage of unused address space. * Up to 8 x 8 pixel characters when REG[00h] bit 2 = 0 and 8 x 16 characters when REG[00h] bit 2 = 1 * Can be mapped anywhere in display memory address space if used with the character generator ROM (REG[00h] bit 0 = 0) Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 98 Epson Research and Development Vancouver Design Center 13.2 Setting the Character Generator Address The CGRAM addresses in the display memory address space are not mapped directly from the address in the Character Generator RAM Start Address registers, REG[19h] REG[1Ah]. The data to be displayed is at a CGRAM address calculated from (REG[19h] REG[1Ah]) + character code + ROW select address. For the ROW select address, see Figure 13-1 "Row Select Address," on page 99. The following tables show the address mapping for CGRAM addresses. Table 13-1 Character Fonts Where Number of Lines 8 (REG[00h] bit 2 = 0) SAG Character Code +ROW Select Address CGRAM Address A15 A14 A13 A12 A11 A10 0 0 0 0 0 0 0 0 0 0 D7 0 A9 D6 0 A8 D5 0 VA8 A7 D4 0 VA7 A6 D3 0 VA6 A5 D2 0 VA5 A4 D1 0 VA4 A3 D0 0 VA3 A2 0 R2 VA2 A1 0 R1 VA1 A0 0 R0 VA0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 Table 13-2 Character Fonts Where Number of Lines 16 (REG[00h] bit 2 = 1) SAG Character Code +ROW Select Address CGRAM Address A15 A14 A13 A12 A11 A10 0 0 0 0 0 0 0 0 D7 0 D6 0 A9 D5 0 A8 D4 0 VA8 A7 D3 0 VA7 A6 D2 0 VA6 A5 D1 0 VA5 A4 D0 0 VA4 A3 0 R3 VA3 A2 0 R2 VA2 A1 0 R1 VA1 A0 0 R0 VA0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 99 Row Row 0 Row 1 Row 2 R3 0 0 0 R2 0 0 0 R1 0 0 1 R0 0 1 0 Line 1 Line 2 Row 7 Row 8 0 1 1 0 1 0 1 0 Row 14 Row 15 1 1 1 1 1 1 0 1 Figure 13-1 Row Select Address Note Lines = 1: lines in the character bitmap 8. Lines = 2: lines in the character bitmap 9. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 100 Epson Research and Development Vancouver Design Center 13.2.1 CGRAM Addressing Example Example 1: Define a pattern for the "A" in Figure 12-1 on page 79. The CGRAM table start address is 4800h. The character code for the defined pattern is 80h (the first character code in the CGRAM area). As the character codes in Figure 13-2 "On-Chip Character Codes," on page 101 show, codes 80h to 9Fh and E0h to FFh are allocated to the CGRAM and can be used as desired. 80h is the first code for the CGRAM. As characters cannot be used if only using graphics mode, there is no need to set the CGRAM data. Table 13-3 Character Data Example CGRAM ADR P1 P2 CSRDIR CSRW P1 P2 MWRITE P P2 P3 P4 P5 P6 P7 P8 P9 5Ch 00h Reverse the CGRAM address calculation to calculate SAG 40h 4Ch Set cursor shift direction to right 46h 00h CGRAM start address is 4800h 48h 42h 70h Write ROW 0 data 88h Write ROW 1 data 88h Write ROW 2 data 88h Write ROW 3 data F8h Write ROW 4 data 88h Write ROW 5 data 88h Write ROW 6 data 00h Write ROW 7 data 00h Write ROW 8 data P16 00h Write ROW 15 data S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 101 13.3 Character Codes The following figure shows the character codes and the codes allocated to CGRAM. All codes can be used by the CGRAM if not using the internal ROM, but the CGRAM address must be set to 0. Upper 4 bits Lower 4 bits 0 1 2 3 4 5 6 7 8 9 A B C D E F ! " # $ % & ' ( ) * + , . / 0 1 2 3 4 5 6 ' a b c d e f 7 p q r s t u v w x y z { | } 8 9 A B C D E F 0@P 1 2 3 4 5 6 7 8 9 : ; < = > ? A B C D E F Q R S T U V GWg H I J K L M N O X Y Z [ ] ^ _ h i j k l m n o CGRAM2 CGRAM1 Figure 13-2 On-Chip Character Codes Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 102 Epson Research and Development Vancouver Design Center 14 Microprocessor Interface 14.1 System Bus Interface CNF[4:0], A[15:1], A0, D[7:0], RD#, WR#, AS and CS are used as control signals for the microprocessor data bus. A0 is normally connected to the lowest bit of the system address bus. CNF[4:2] change the operation of the RD# and WR# pins to enable interfacing to either a Generic (Z80), M6800, or MC68K family bus, and should be pulled-up or pulleddown according to Table 5-6: "Summary of Configuration Options," on page 24. 14.1.1 Generic The following table shows the signal states for each function. Table 14-1 Generic Interface Signals A0 1 0 1 RD# 0 1 1 WR# 1 0 0 Function Display data and cursor address read Display data and parameter write Command write 14.1.2 M6800 Family The following table shows the signal states for each function. Table 14-2 M6800 Family Interface Signals A0 1 0 1 R/W# 1 0 0 E 1 1 1 Function Display data and cursor address read Display data and parameter write Command write 14.1.3 MC68K Family The following table shows the signal states for each function. Table 14-3 M6800 Family Interface Signals A0 1 0 1 RD/WR# LDS# 1 0 0 0 0 0 Function Display data and cursor address read Display data and parameter write Command write S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 103 15 Application Notes 15.1 Register Initialization/Initialization Parameters Square brackets around a parameter name indicate the number represented by the parameter, rather than the value written to the parameter register. For example, [FX] = FX + 1. 15.1.1 SYSTEM SET Command and Parameters * FX The horizontal character field size is determined from the horizontal display size in pixels [VD] and the number of characters per line [VC]. [VD] / [VC] = [FX] * C/R C/R can be determined from VC and FX. [C/R] = RND ([FX] / 8) [VC] Where RND(x) denotes rounded up to the next highest integer. [C/R] is the number of bytes per line, not the number of characters. * TC/R TC/R must satisfy the condition [TC/R] [C/R] + 2. * fSYSCLK and fFR Once TC/R has been set, the frame frequency, fFR, and lines per frame [L/F] will also have been set. The oscillator frequency fSYSCLK is given by: fSYSCLK = ([ClockDiv] x [bpp] x [TC/R'] x [FX] x [L/F] x Ffr) / 4 where: ClockDiv bpp Ffr 4, 8, or 16 1, 2, or 4 Frame Rate Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 104 Epson Research and Development Vancouver Design Center To determine the values for TC/R', the following formulas must also be calculated. A = (CR + 1) x (FX + 1) / 4 B = (A / 16) C = 16 x B x 8 / (FX + 1) C = 16 x B x 16 / (FX + 1) D = (TC/R - CR) x 2 TC/R' = (C + D) / 2 round up to the nearest integer (when [FX] 8) (when [FX] > 8) * If no standard crystal close to the calculated value of fOSC exists, a higher frequency crystal can be used and the value of TC/R revised using the above equation. * Symptoms of an incorrect TC/R setting are listed below. If any of these appears, check the value of TC/R and modify it if necessary. * Vertical scanning halts and a high-contrast horizontal line appears. * All pixels are on or off. * The FPLINE output signal is absent or corrupted. * The display is unstable. Table 15-1 Panel Calculations Product Resolution (X x Y 256 x 64 [FX] [FY] [C/R] [TC/R] 24h fOSC (MHz) See note 2 [FX] = 6 pixels: [C/R] = 42 = 2Ah bytes: 8 or 16, depending 256 / 6 = 42 remainder 4 C/R = 29h. When using HDOT on the screen = 4 blank pixels SCR, [C/R] = 43 bytes [FX] = 6 pixels: [C/R] = 85 = 55h bytes: 8 or 16, depending 512 / 6 = 85 remainder 2 C/R = 54h. When using HDOT on the screen = 2 blank pixels SCR, [C/R] = 86 bytes [FX] = 8 pixels: [C/R] = 32 = 20h bytes: 8 or 16, depending 256 / 8 = 32 remainder 0 C/R = 19h. When using HDOT on the screen = no blank pixels SCR, [C/R] = 33 bytes [C/R] = 102 = 66h bytes: [FX] = 10 pixels: 8 or 16, depending C/R = 65h. When using HDOT 256 / 10 = 51 remainder 2 on the screen SCR, [C/R] = 103 bytes = 2 blank pixels 1 512 x 64 62h 2.66 256 x 128 16h 1.84 512 x 128 78h 20 Note 1 The remaining pixels on the right-hand side of the display are automatically blanked by the S1D13700. There is no need to zero the display memory corresponding to these pixels. 2 Assumes a frame frequency of 70 Hz, 1 bpp, and a clock divide of 4. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 105 15.1.2 Initialization Example The initialization example shown below is for a S1D13700 with an 8-bit microprocessor interface bus and an Epson EG4810S-AR display unit (512 x 128 pixels). Indirect Addressing Start Clear first memory layer Clear second memory layer CSRW Supply on SYSTEM SET SCROLL CSR FORM HDOT SCR DISP ON Output display data OVLAY DISP OFF Figure 15-1 Initialization Procedure Note Set the cursor address to the start of each screen's layer memory, and use MWRITE to fill the memory with space characters, 20h (text screen only) or 00h (graphics screen only). Determining which memory to clear is explained in Section 15.1.3, "Display Mode Setting Example 1: Combining Text and Graphics" on page 110. Table 15-2 Indirect Addressing Initialization Procedure No. 1 2 3 Command Power-up Supply SYSTEM SET C = 40h P1 = 38h M0: Internal CGROM (REG[00h] bit 0) M2: 8 lines per character (REG[00h] bit 2) W/S: Two-panel drive (REG[00h] bit 3) IV: Sets top-line compensation to none (REG[00h] bit 5) P2 = 87h FX: Horizontal character size = 8 pixels (REG[01h] bits 3-0) MOD: Two-frame AC drive (REG[01h] bit 7) Operation Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 106 Epson Research and Development Vancouver Design Center Table 15-2 Indirect Addressing Initialization Procedure (Continued) No. Command P3 = 07h P4 = 3Fh P5 = 49h P6 = 7Fh P7 = 80h P8 = 00h 4 SCROLL C = 44h P1 = 00h P2 = 00h P3 = 40h P4 = 00h P5 = 10h P6 = 40h P7 = 00h P8 = 04h P9 = 00h P10 = 30h First screen block start address (REG[0Bh] bits 7-0, REG[0Ch] bits 7-0) Set to 0000h Display lines in first screen block = 64 (REG[0Dh] bits 7-0) Second screen block start address (REG[0Eh] bits 7-0, REG[0Fh] bits 7-0) Set to 1000h Display lines in second screen block = 64 (REG[10h] bits 7-0) Third screen block start address (REG[11h] bits 7-0, REG[12h] bits 7-0) Set to 0400h Fourth screen block start address (REG[13h] bits 7-0, REG[14h] bits 7-0) Set to 3000h Display memory (SAD1) 0000h (SAD3) 0400h 0800h (SAD2) 1000h 3rd display memory page (SAD4) 3000h 4th display memory page 5000h 1st display memory page 2nd display memory page Operation FY: Vertical character size = 8 pixels (REG[02h] bits 3-0 C/R: 64 display addresses per line (REG[03h] bits 7-0) TC/R: Total address range per line = 90 (REG[04h] bits 7-0) fOSC = 6.5 MHz, fFR = 70 Hz L/F: 128 display lines (REG[05h] bits 7-0 AP: Virtual screen horizontal size is 128 addresses (REG[06h] bits 7-0, REG[07h] bits 7-0) 5 HDOT SCR C = 5Ah P1 = 00h Set horizontal pixel shift to zero (REG[1Bh] bits 2-0) 6 OVLAY C = 5Bh P1 = 01h MX 1, MX 0: Inverse video superposition (REG[18h] bits 1-0) DM 1: First screen block is text mode (REG[18h] bit 2) DM 2: Third screen block is text mode (REG[18h] bit 3) S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 107 Table 15-2 Indirect Addressing Initialization Procedure (Continued) No. 7 Command DISP ON/OFF C = 58h P1 = 56h FP1, FP0: FP3, FP2: FP5, FP4: 8 9 D: Display OFF (REG[09h] bit 0) FC1, FC0: Flash cursor at 2 Hz (REG[0Ah] bits 1-0) First screen block ON (REG[0Ah] bits 3-2) Second and fourth screen blocks ON (REG[0Ah] bits 5-4) Third screen block ON (REG[0Ah] bits 7-6) Operation Clear data in first layer Fill first screen layer memory with 20h (space character) Clear data in second Fill second screen layer memory with 00h (blank data) layer Display Character code in every position 1st layer Blank code in every position 2nd layer 10 CSRW C = 46h P1 = 00h P2 = 00h Set cursor to start of first screen block (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0) 11 CSR FORM C = 5Dh P1 = 04h P2 = 86h CRX: Horizontal cursor size = 5 pixels (REG[15h] bits 3-0) CRY: Vertical cursor size = 7 pixels (REG[16h] bits 3-0) CM: Block cursor (REG[16h] bit 7) 12 DISP ON/OFF C = 59h Display ON Display 13 14 CSR DIR C = 4Ch MWRITE C = 42h P1 = 20h P2 = 45h P3 = 50h P4 = 53h `' `E' `P' `S' Set cursor shift direction to right (REG[17h] bits 1-0) Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 108 Epson Research and Development Vancouver Design Center Table 15-2 Indirect Addressing Initialization Procedure (Continued) No. Command P5 = 4Fh P6 = 4Eh `O' `N' Operation EPSON 15 CSRW C = 46h P1 = 00h P2 = 10h Set cursor to start of second screen block (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0) 16 17 CSR DIR C = 4Fh MWRITE C = 42h P1 = FFh P9 = FFh Fill in a square to the left of the `E' Set cursor shift direction to down (REG[17h] bits 1-0) EPSON 18 CSRW C = 46h P1 = 01h P2 = 10h Set cursor address to 1001h (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0) 19 MWRITE C = 42h P1 = FFh P9 = FFh Fill in the second screen block in the second column of line 1 20 CSRW Repeat operations 18 and 19 to fill in the background under `EPSON' (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0) S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 109 Table 15-2 Indirect Addressing Initialization Procedure (Continued) No. Command Inverse display Operation EPSON 29 30 MWRITE CSRW C = 46h P1 = 00h P2 = 01h Set cursor to line three of the first screen block (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0) 31 32 CSR DIR C = 4Ch MWRITE C = 42h P1 = 44h P2 = 6Fh P3 = 74h P4 = 20h P5 = 4Dh P6 = 61h P7 = 74h P8 = 72h P9 = 69h P10 = 78h P11 = 20h P12 = 4Ch P13 = 43h P14 = 44h `D' `o' `t' `' `M' `a' `t' `r' `i' `x' `' `L' `C' `D' Inverse display Set cursor shift direction to right (REG[17h] bits 1-0) EPSON Dot matrix LCD Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 110 Epson Research and Development Vancouver Design Center 15.1.3 Display Mode Setting Example 1: Combining Text and Graphics Conditions * 320 x 200 pixels, single panel drive (1/200 duty cycle) * First layer: text display * Second layer: graphics display * 8 x 8-pixel character font * CGRAM not required Display memory allocation * First layer (text): 320 / 8 = 40 characters per line, 200 / 8 = 25 lines. Required memory size = 40 x 25 = 1000 bytes. * Second layer (graphics): 320 / 8 = 40 characters per line, 200 / 1 = 200 lines. Required memory size = 40 x 200 = 8000 bytes. 03E8h 2nd graphics layer (8000 bytes) 0000h 1st character layer (1000 bytes) 2327h 03E7h Figure 15-2 Character Over Graphics Layers S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 111 Register Setup Procedure SYSTEM SET C = 40h P1 = 30h P2 = 87h P3 = 07h P4 = 27h P5 = 34h P6 = C7h P7 = 28h P8 = 00h SCROLL C = 44h P1 = 00h P2 = 00h P3 = C8h P4 = E8h P5 = 03h P6 = C8h P7 = Xh P8 = Xh P9 = Xh P10 = Xh CSRFORM C = 5Dh P1 = 04h P2 = 86h HDOT SCR C = 5Ah P1 = 00h OVLAY C = 5Bh P1 = 00h DISP ON/OFF C = 59h P1 = 16h X = Don't care [TC/R] = 52, so TC/R = 34h fOSC = 6 MHz (refer to Section 15.1.1, "SYSTEM SET Command and Parameters" on page 103) fFR = 70 Hz (refer to Section 15.1.1, "SYSTEM SET Command and Parameters" on page 103) TC/R calculation Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 112 Epson Research and Development Vancouver Design Center 15.1.4 Display Mode Setting Example 2: Combining Graphics and Graphics Conditions * 320 x 200 pixels, single-panel drive (1/200 duty cycle) * First layer: graphics display * Second layer: graphics display Display memory allocation * First layer (graphics): 320 / 8 = 40 characters per line, 200 / 1 = 200 lines. Required memory size = 40 x 200 = 8000 bytes. * Second layer (graphics): 320 / 8 = 40 characters per line, 200 / 1 = 200 lines. Required memory size = 8000 bytes. 1F40h 2nd graphics layer (8000 bytes) 0000h 1st graphics layer (8000 bytes) 3E7Fh 1F3Fh Figure 15-3 Two-Layer Graphics S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 113 Register setup procedure SYSTEM SET C = 40h P1 = 30h P2 = 87h P3 = 07h P4 = 27h P5 = 34h P6 = C7h P7 = 28h P8 = 00h SCROLL C = 44h P1 = 00h P2 = 00h P3 = C8h P4 = 40h P5 = 1Fh P6 = C8h P7 = Xh P8 = Xh P9 = Xh P10 = Xh CSRFORM C = 5Dh P1 = 07h P2 = 87h HDOT SCR C = 5Ah P1 = 00h OVLAY C = 5Bh P1 = 0Ch DISP ON/OFF C = 59h P1 = 16h X = Don't care [TC/R] = 52, so TC/R = 34h fOSC = 6 MHz (refer to Section 15.1.1, "SYSTEM SET Command and Parameters" on page 103) fFR = 70 Hz (refer to Section 15.1.1, "SYSTEM SET Command and Parameters" on page 103) TC/R calculation Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 114 Epson Research and Development Vancouver Design Center 15.1.5 Display Mode Setting Example 3: Combining Three Graphics Layers Conditions * 320 x 200 pixels, single-panel drive (1/200 duty cycle) * First layer: graphics display * Second layer: graphics display * Third layer: graphics display Display memory allocation * All layers (graphics): 320 / 8 = 40 characters per line, 200 / 1 = 200 lines. Required memory size = 40 x 200 = 8000 bytes. 3E80h 3rd graphics layer (8000 bytes) 1F40h 2nd graphics layer (8000 bytes) 5DBFh 0000h 1st graphics layer (8000 bytes) 3E7Fh 1F3Fh Figure 15-4 Three-Layer Graphics S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 115 Register setup procedure SYSTEM SET C = 40h P1 = 30h P2 = 87h P3 = 07h P4 = 27h P5 = 34h P6 = C7h P7 = 28h P8 = 00h SCROLL C = 44h P1 = 00h P2 = 00h P3 = C8h P4 = 40h P5 = 1Fh P6 = C8h P7 = 80h P8 = 3Eh P9 = Xh P10 = Xh CSR FORM C = 5Dh P1 = 07h P2 = 87h HDOT SCR C = 5Ah P1 = 00h OVLAY C = 5Bh P1 = 1Ch DISP ON/OFF C = 59h P1 = 16h X = Don't care [TC/R] = 52, so TC/R = 34h fOSC = 6 MHz (refer to Section 15.1.1, "SYSTEM SET Command and Parameters" on page 103) fFR = 70 Hz (refer to Section 15.1.1, "SYSTEM SET Command and Parameters" on page 103) TC/R calculation Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 116 Epson Research and Development Vancouver Design Center 15.2 System Overview Section 3, "System Diagrams" on page 14 shows some typical S1D13700 implementations where the microprocessor issues instructions to the S1D13700, and the S1D13700 drives the LCD panel. Since the S1D13700 integrates all required LCD control circuits, minimal external components are required to construct a complete medium- resolution liquid crystal display solution. 15.3 Smooth Horizontal Scrolling The S1D13700 supports smooth horizontal scrolling to the left as shown in Figure 15-5 "HDOT SCR Example," on page 117. When scrolling left, the screen is effectively moving to the right over the larger virtual screen. Instead of changing the screen block start address (SADx) and shifting the display by eight pixels, smooth scrolling is achieved by repeatedly changing the horizontal pixel scroll parameter of the HDOT SCR command (REG[1Bh] bits 2-0). When the display has been scrolled seven pixels, the horizontal pixel scroll parameter is reset to zero and screen block start address is incremented by one. Repeating this operation at a suitable rate gives the appearance of smooth scrolling. Note To scroll the display to the right, the procedure is reversed. When the edge of the virtual screen is reached, the microprocessor must take appropriate steps to avoid corrupting the display. For example, scrolling must be stopped or the display must be modified. Note The HDOT SCR command cannot be used to scroll individual layers. Note When in 2 bpp or 4 bpp mode, smooth horizontal scrolling in pixel units is not supported. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 117 HDOT SCR parameter SAD SAD + 1 SAD + 2 P1 = 00h Magnified AP P1 = 01h SAD = SAD P1 = 02h Display P1 = 03h C/R Virtual screen P1 = 07h P1 = 00h SAD = SAD + 1 Not visible Visible Where: AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0) C/R = character bytes per row (REG[03h] bits 7-0) Figure 15-5 HDOT SCR Example Note The response time of LCD panels changes considerably at low temperatures. Smooth scrolling under these conditions may make the display difficult to read. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 118 Epson Research and Development Vancouver Design Center 15.4 Layered Display Attributes S1D13700 incorporates a number of functions for enhancing displays using monochrome LCD panels. It allows the display of inverse characters, half-intensity menu pads and flashing of selected screen areas. These functions are controlled by REG[18h] Overlay Register and REG[0Ah] Display Attribute Register. Attribute MX1 MX0 Combined Layer Display 1st Layer Display 2nd Layer Display Reverse 0 1 IV EPSON IV EPSON Half-tone 0 0 ME Yes, No ME Yes, No 0 0 1 0 1 BL Error BL Error Local flashing 0 0 0 Ruled line RL LINE LINE RL LINE LINE Figure 15-6 Layer Synthesis These effects can be achieved in different ways, depending on the display configuration. The following sections describe these functions. Note Not all functions can be used in one layer at the same time. 15.4.1 Inverse Display For inverse display where the first layer is text and the second layer is graphics. 1. CSRW, CSRDIR, MWRITE Write to the graphics screen at the area to be inverted. 2. OVLAY: MX0 = 1, MX1 = 0 (REG[18h] bits 1-0) Set the layer compensation method of the two layers to Exclusive-OR. 3. DISP ON/OFF: FP0 = 1, FP1 = 0, FP2 = 1, FP3 = 0. Turn on layers 1 and 2 with no flashing. S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 119 15.4.2 Half-Tone Display The FP parameter (display attributes) can be used to generate a half-intensity display by flashing the display at 17Hz. Note that this mode may cause flicker problems with certain LCD panels. Menu Pad Display Turn flashing off for the first layer, on at 17 Hz for the second layer, and combine the screens using the OR function. 1. REG[18h] Overlay Register = 00h 2. REG[0Ah] Display Attribute Register = 34h SAD1 AB + SAD2 AB Half-tone 1st layer 2nd layer Combined layer display Figure 15-7 Half-Tone Character And Graphics Graph Display To display two overlaid graphs on the screen, configure the display in the same manner as for menu pad display and put one graph on each screen layer. The difference in contrast between the half and full intensity displays make it easy to distinguish between the two graphs and create an attractive display. 1. REG[18h] Overlay Register = 00h 2. REG[0Ah] Display Attribute Register = 34h Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 120 Epson Research and Development Vancouver Design Center 15.4.3 Flash Attribute Small Area To flash selected characters, the MPU can alternately write the characters as character codes and blank characters at intervals of 0.5 to 1.0 seconds. Large Area Divide both layer 1 and layer 2 into two screen blocks each, layer 2 being divided into the area to be flashed and the remainder of the screen. Flash the layer 2 screen block at 2 Hz for the area to be flashed and combine the layers using the OR function. ABC ABC XYZ XYZ Figure 15-8 Flash Attribute for a Large Area S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 121 15.5 16 x 16-Dot Graphic Display 15.5.1 Command Usage To display 16 x 16 pixel characters, use the following procedure. 1. Set the cursor address, REG[1Ch] - REG[1Dh] 2. Set the cursor shift direction, REG[17h] bits 1-0 3. Write to the display memory 15.5.2 Kanji Character Display To write large characters, use the following procedure. For further information, see the flowchart in Figure 15-9 "Graphics Address Indexing," on page 122. 1. Reads the character data from the CGRAM 2. Set the display address 3. Writes to the display memory Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 122 Epson Research and Development Vancouver Design Center A0 = 0 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh O8 O7 O6 O5 O4 O3 O2 O1 (1) (3) (5) (7) (9) (11) (13) (15) (17) (19) (21) (23) (25) (27) (29) (31) 1st column Scan address A1 to A4 A0 = 1 O8 O7 O6 O5 O4 O3 O2 O1 (2) (4) (6) (8) (10) (12) (14) (16) (18) (20) (22) (24) (26) (28) (30) (32) 2nd column CGROM output (n) shows the CG data readout order (Kanji pattern) (6) (4) (2) 2nd column memory area (19) (17) (15) (13) (11) (9) (7) (5) (3) (1) Data held in the microprocessor memory (4) (2) 1st column memory area (3) (1) Data written into the S1D13700 display memory Figure 15-9 Graphics Address Indexing S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 123 320 dots Direction of cursor movement (1) (3) (5) (7) (9) (11) (13) (15) (17) (19) (21) (23) (25) (27) (29) (31) (2) (4) (6) (8) (10) (12) (14) (16) (18) (20) (22) (24) (26) (28) (30) (32) 240 dots Figure 15-10 Graphics Bit Map Using an external character generator RAM an 8 x 16 pixel font can be used, which allows a 16 x 16 pixel character to be displayed in two segments. The CGRAM data format is described in Figure 13 "Character Generator," on page 97. This allows the display of up to 128, 16 x 16 pixel characters. If CGRAM is also used, 96 fixed characters and 32 bankswitchable characters are also be supported. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 124 Epson Research and Development Vancouver Design Center For Direct Addressing Mode Start Enable cursor downwards movement Set column 1 cursor address Write data Set column 2 cursor address Write data End For Indirect Addressing Mode Start Enable cursor downwards movement Set column 1 cursor address Write data Set column 2 cursor address Write data End Figure 15-11 16 x 16-Dot Display Flowchart S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 125 16 Internal Character Generator Font Character code bits 0 to 3 5 6 7 8 9 A 0 2 3 4 Character code bits 4 to 7 5 6 7 A B C D 1 1 2 3 4 B C D E F Figure 16-1 On-Chip Character Set Note The shaded positions indicate characters that have the whole 6 x 8 bitmap blackened. Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 126 Epson Research and Development Vancouver Design Center 17 Power Save Mode The S1D13700 supports a power save mode that places it into a power efficient state. Power save mode is controlled by the Power Save Mode Enable bit, REG[08h] bit 0. The S1D13700 enters power save mode at least one blank frame after the enable bit is set. When power save mode is enabled, blank data is sent to the X-drivers, and the Y-drivers have their bias supplies turned off by the YDIS signal. Using the YDIS signal to disable the Y-drivers guards against any spurious displays. The internal registers of the S1D13700 maintain their values during the power save state and the display memory control pins maintain their logic levels to ensure that the display memory is not corrupted. The S1D13700 is removed from power save mode by writing a 0 the Power Save Mode Enable bit, REG[08h] bit 0. However, after disabling power save mode, one dummy write to any register must be performed for direct addressing mode, and at least two dummy writes must be performed for indirect addressing mode. For indirect addressing mode, the POWER SAVE command has no parameter bytes. For indirect addressing mode, the SYSTEM SET command exits power save mode. 1. The YDIS signal goes LOW between one and two frames after the power save command is received. Since YDIS forces all display driver outputs to go to the deselected output voltage, YDIS can be used as a power down signal for the LCD unit. This can be done by having YDIS turn off the relatively high power LCD drive supplies at the same time as it blanks the display. 2. Since all internal clocks in the S1D13700 are halted while power save mode is enabled, a DC voltage is applied to the LCD panel if the LCD drive supplies remain on. If reliability is a prime consideration, turn off the LCD drive supplies before issuing the power save command. 3. The bus lines become high impedance when power save mode is enabled. If the bus is required to be a known state, pull-up or pull-down resistors can be used. Table 17-1 State of LCD Pins During Power Save Mode LCD Pin YDIS FPFRAME YSCL MOD FPLINE XECL FPSHIFT FPDAT[3:0] WAIT# DB[7:0] XCD1 State During Display Off Low Low High Low Low Low Low Low Hi-Z Hi-Z High State During Power Save Mode Low Low High Low Low Low Low Low Hi-Z Hi-Z High S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 127 18 Mechanical Data All dimensions in mm 120.4 10.20.1 48 33 49 32 10.20.1 64 17 1 1.00.1 0.5 0.20.03 16 1.2max 0.1 1.0 0.50.2 0 to 10 0.150.05 Figure 18-1 Mechanical Drawing TQFP13 - 64 pin Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 120.4 S1D13700 X42A-A-001-00 Page 128 Epson Research and Development Vancouver Design Center 19 References The following documents contain additional information related to the S1D13700. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. 20 Technical Support Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp/ North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com/ Taiwan Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan Tel: 02-2717-7360 Fax: 02-2712-9164 http://www.epson.com.tw/ Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 http://www.epson.com.sg/ Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk/ Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 http://www.epson-electronics.de/ S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 129 Change Record X42A-A-001-01 Revision 1.0 * released as revision 1.0 X42A-A-001-00 Revision 0.07 * section 5.2, updated reset state to "Z" for CNF[4:0], A[15:0], RD#, WR#, CS#, AS#, RESET#, XCG1, and CLKI * table 5-7, updated host pin mapping for generic direct/indirect, AS# should be connected to HIOVDD * table 6-5, in DC Characteristics for VOH/VOL: cell type changed from "CS2" to "CB2" * table 7-8, in LCD AC Timing, t6 min and max for both 3.3 and 5.0 volts changed to 0ns for min and 4ns for max * REG[16h] bit 7, fixed block style cursor example * table 15-1, for 256x64 [TC/R] should be 24h and for 256x128 [TC/R] should be 16h X42A-A-001-00 Revision 0.06 * section 1.2, clarified character generator options * section 2.5, clarified character generator options * section 2.7, changed input clock max to 60MHz and pixel clock max to 15MHz * section 2.7, changed max pixel clock to max FPSHIFT clock * section 2.8, added lead free package * figures 3-1, 3-2, 3-5, corrected AS# signal to be pulled up to VDD * figures 3-3 and 3-4, updated system diagrams for MC68K implementations to show AS# ORed with CS# * section 4, removed TESTEN from the diagram and XCG1/XCD1 no longer are shown connecting to the Host * section 5.2.1, * changed A[15:1], A0, D[7:0] RESET# state to "0 or Z" * changed CNF[4:0] RESET# state to "Z" * changed WAIT# cell type to HTB2T * changed RESET# reset state to "1" * changed AS# to be pulled up to VDD for Generic and M6800 interfaces * changed SCANEN pin description to be "...must be connected to ground..." instead of "...must be left unconnected and floating..." * section 5.2.3, changed XCG1 and XCD1 power to COREVDD Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 130 Epson Research and Development Vancouver Design Center * section 5.2.3, changed CLKI power to HIOVDD * section 5.4, changed WAIT# pin mapping to WAIT#/DTACK# or unconnected for indirect interfaces * table 6-2, changed NIOVin max to NIOVDD instead of HIOVDD * table 6-3, changed Voh min to VDD-0.4 instead of HIOVDD-0.4 * table 6-4, removed Vih2/Vil2 and renamed Vih1/Vil1 to Vih/Vil, also renamed Vh1 to Vh * table 6-5, added new tables that references the cell types associated with each electrical characteristic * section 7, added note about pin capacitance * section 7.2, changed RES to RESET# * section 7.3, updated CPU Interface timing to Generic Direct/Indirect with/without WAIT# and MC68K Direct/Indirect with/without WAIT# * section 7.3.1, for t11/t12 changed "...WAIT# is/is not asserted..." to "...WAIT# is/is not used..." * section 7.3.3, for t11/t12 changed "...WAIT# is/is not asserted..." to "...WAIT# is/is not used..." * section 7.4, updated Power Save Mode/Display Enable Timng parameters and values * section 7.5, updated LCD timing diagrams and added 2 new parameters * section 8, removed the CGROM area from the memory map * section 9.1, updated clock diagram, added CLKI/OSC logic * section 9.2, added descriptions for system clock and FPSHIFT clock * REG[00h] bit 4, changed bit to "reserved with a default of 1" * REG[00h] bit 3, removed diagram for left and right dual panel display * REG[00h] bit 3, updated note about adjusting SL to compensate for the shift in characters * REG[00h] bit 0, updated Character Generator Select bit to mention that if the CGROM is used, the CGRAM can only support up to 64 8x8 characters * REG[02h], removed comment about setting to 00h when graphics mode is enabled * REG[03h], updated bit description and added reference to C/R formulas * REG[04h], updated bit description and added reference to TC/R formulas * REG[0Ah] bits 1-0, changed frequency of option 10 to "...(approx 2Hz)..." * REG[0Ah] bits 7-2, seperated the Display Attribute bits for each address block * REG[17h], clarified the possible movement for the Cursor Shift Direction bits * REG[18h] bit 4, changed bit name from "Overlay Select" to "3 Layer Overlay Select" S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 131 * REG[18h] bits 3-2, split these bits into individual display mode bits for screen block 3 and 1 * REG[1Bh], changed wording of Horizontal Pixel Scroll bit description * REG[1Ch]-[1Dh], updated the bit description for the CSRW bits * REG[1Eh]-[1Fh], updated bit description * section 11, changed number of bytes for DISP ON/OFF from 2 to 1 * section 11, changed Parameter Read from 101 to 110 and Parameter Write from 010 to 001 * section 11.1.1, moved fOSC formulas to section 15.1.1 * section 11.1.3, updated display on parameters and added display off parameters * section 11.1.3, fixed display on/off parameters, display off is 01011000 and display on is 01011001 * section 11.1.6, updated cursor direction parameters * section 11.1.9, updated Hdot Scr parameters * section 12.2.1, added "...in 1 bpp." * section 12.2.2, expanded note under figure 12-5 to describe all color depths * figure 12-6, changed line notation between upper and lower panel to be clearer * section 15.1.1, changed TC/R restriction to TC/R >= C/R + 2 instead of C/R + 4 * table 15-1, updated TC/R values in table and fosc values * table 15-2, for P5 = 49h changed fOSC from 6.0MHz to 6.5MHz * section 15.1.3, updated register setup procedure table * section 15.1.4, updated register setup procedure table * section 15.1.5, updated register setup procedure table * figure 15-5 and 15-6, changed FPFRAMEIS to YDIS * section 15.3, removed "system Interconnection" section as redundant * section 15.4, removed the MX1=1, MX0=1 options from the diagram Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 132 Epson Research and Development Vancouver Design Center X42A-A-001-00 Revision 0.05 * section 5.2.1 and 5.2.2, confirmed RESET# states for all pins * section 5.2, clarified pin descriptions and "standardized" them to normal 13xxx descriptions where possible * section 5.3, removed all references regarding CNF pins being latched at the rising edge of RESET# * section 5.4, completed the host bus interface pin mapping table * section 7.5, updated LCD timing table parameters t6,t7, and removed parameters t11 and t14 * REG[00h] bit 1, removed M1 bit and all references * REG[01h], reworded the bit description for the FX bits * REG[03h], added reference to section 11.1.2 and fOSC formula * REG[08h], updated the power save mode enable bit and moved the extra information about power save mode to section 19 * REG[09h], updated bit description for Display Enable bit and added cross reference to LCD pin state table * REG[0Ah] bits 5-0, clarified screen block attributes table * REG[0Ah] bits 1-0, added note about writing and reading to/from memory while the cursor is disabled * REG[18h] bits 1-0, reserved the Priority-OR function * section 11.1.2, added formulas for determining fOSC and Frame Rate * section 17, added table listing the state of all LCD pins during Power Save mode as per etr i42bl001 S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 Epson Research and Development Vancouver Design Center Page 133 X42A-A-001-00 Revision 0.04 * section 5.2, add RESET# State to all pins * section 5.2.1 Host Interface - in table 5-1, description for pin A0, removed the 3 truth tables for Generic, M6800 and MC68K * section 6 D.C. Characteristics - change Topr "min = -40" and "max = 85" * REG[00h] bit 0 - change second paragraph in description to read "... mapped at the CG Start Address, REG[1Ah] and REG[19h]" * REG[03h] - delete "The number of excess pixels must not exceed 64" from description * REG[08h} bit 0 - add "Entering power save also clears the Display-On..." to bit description * REG[08h} bit 0 - add "in Direct mode, performing one dummy..." to bit description * REG[16h bits 3-0 - add "These bits must be set less than or equal to FY." to bit description * REG[17h] bits 1-0 - add indirect mode commands to table * REG[19h], REG[1Ah] - delete note, rewrite description * REG[1Ch], REG[1Dh] - mark registers as Write Only * CSRR (REG[1E], REG[1Fh]) - delete text "These registers are used only in Indirect Addressing mode" * REG[1E], REG[1Fh] - mark registers as Read Only * table 11-2 Indirect Addressing Command/Write/Read - change Parameter Read [P#] to 101b * section 15.3.1 S1D13700 - in figures 15-5 and 15-6 correct the Crystal connections * Hardware Functional Specification Issue Date: 2004/01/06 Revision 1.0 S1D13700 X42A-A-001-00 Page 134 Epson Research and Development Vancouver Design Center X42A-A-001-00 Revision 0.03 * section 5.3, revised summary of configuration options table * section 6, updated 3.3V and 5.0V DC Characteristics * section 7, changed Capacitance load to 30pF for Host and LCD * section 7.1.1, changed input clock pwh and pwl to 0.4Tclki * section 7.2, moved reset timing to this section * section 7.3.1, updated Generic Bus Direct Timing diagram and table * section 7.3.2, updated Generic Bus Indirect Timing diagram and table * section 7.3.3, updated MC68K Bus Direct Timing diagram and table * section 7.3.4, updated MC68K Bus Indirect Timing diagram and table * section 7.4, updated power save enable/display enable timing * section 7.5, updated display timings diagrams and table * section 9, updated clock section with diagram and moved oscillator circuit to subsection * section 15, updated Oscillator circuit diagram and added table S1D13700 X42A-A-001-00 Revision 1.0 Hardware Functional Specification Issue Date: 2004/01/06 |
Price & Availability of S1D13700
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |